MC9S12C Datasheet, PDF (58/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.4 System Clock Description
The clock and reset generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-14 shows the clock connections from the CRG to all modules. Consult the CRG Block User
Guide for details on clock generation.
Core Clock
S12_CORE
Flash
EXTAL
XTAL
CRG
Bus Clock
Oscillator Clock
Figure 1-14. Clock Connections
RAM
TIM
ATD
PIM
SCI
SPI
MSCAN
Not on 9S12GC
VREG
TPM
1.5 Modes of Operation
Eight possible modes determine the device operating configuration. Each mode has an associated default
memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.5.1 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
58
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23