MC9S12C Datasheet, PDF (450/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Table 15-13. TSCR2 Field Descriptions (continued)
Field
3
TCRE
2
PR[2:0]
Description
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
Bus Clock as shown in Table 15-14.
Table 15-14. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
Bus Clock / 1
0
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
1
Bus Clock / 8
1
0
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
1
0
Bus Clock / 64
1
1
1
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
15.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
R
C7F
W
6
C6F
5
C5F
4
C4F
3
C3F
2
C2F
1
C1F
0
C0F
Reset
0
0
0
0
0
0
0
0
Figure 15-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
450
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23