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| MC9S12C Datasheet, PDF (62/680 Pages) Motorola, Inc – 16-Bit Microcontroller | |||
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
Table 1-9. Interrupt Vector Locations (continued)
Vector Address
Interrupt Source
0xFFDE, 0xFFDF
0xFFDC, 0xFFDD
0xFFDA, 0xFFDB
0xFFD8, 0xFFD9
Standard timer overï¬ow
Pulse accumulator A overï¬ow
Pulse accumulator input edge
SPI
0xFFD6, 0xFFD7
SCI
0xFFD4, 0xFFD5
0xFFD2, 0xFFD3
ATD
0xFFD0, 0xFFD1
0xFFCE, 0xFFCF
Port J
0xFFCC, 0xFFCD
0xFFCA, 0xFFCB
0xFFC8, 0xFFC9
0xFFC6, 0xFFC7
CRG PLL lock
0xFFC4, 0xFFC5
CRG self clock mode
0xFFBA to 0xFFC3
0xFFB8, 0xFFB9
FLASH
0xFFB6, 0xFFB7
CAN wake-up(1)
0xFFB4, 0xFFB5
CAN errors1
0xFFB2, 0xFFB3
CAN receive1
0xFFB0, 0xFFB1
CAN transmit1
0xFF90 to 0xFFAF
0xFF8E, 0xFF8F
Port P
0xFF8C, 0xFF8D
0xFF8C, 0xFF8D
PWM Emergency Shutdown
0xFF8A, 0xFF8B
VREG LVI
0xFF80 to 0xFF89
1. Not available on MC9S12GC Family members
CCR
Mask
Local Enable
I bit
TMSK2 (TOI)
I bit
PACTL (PAOVI)
I bit
PACTL (PAI)
I bit
SPICR1 (SPIE, SPTIE)
I bit
SCICR2
(TIE, TCIE, RIE, ILIE)
Reserved
I bit
ATDCTL2 (ASCIE)
Reserved
I bit
PIEP (PIEP7-6)
Reserved
Reserved
Reserved
I bit
PLLCR (LOCKIE)
I bit
PLLCR (SCMIE)
Reserved
I bit
FCNFG (CCIE, CBEIE)
I bit
CANRIER (WUPIE)
I bit CANRIER (CSCIE, OVRIE)
I bit
CANRIER (RXFIE)
I bit
CANTIER (TXEIE[2:0])
Reserved
I bit
Reserved
I bit
I bit
Reserved
PIEP (PIEP7-0)
PWMSDN(PWMIE)
CTRL0 (LVIE)
HPRIO Value
to Elevate
0x00DE
0x00DC
0x00DA
0x00D8
0x00D6
0x00D2
0x00CE
0x00C6
0x00C4
0x00B8
0x00B6
0x00B4
0x00B2
0x00B0
0x008E
0x008C
0x008A
62
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23
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