MC9S12C Datasheet, PDF (102/680 Pages) Motorola, Inc – 16-Bit Microcontroller

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.6.3 Port AD Data Direction Register (DDRAD)
Module Base + 0x0032
7
R
DDRAD7
W
Reset
0
Read: Anytime.
Write: Anytime.
6
DDRAD6
5
DDRAD5
4
DDRAD4
3
DDRAD3
2
DDRAD2
0
0
0
0
0
Figure 2-42. Port AD Data Direction Register (DDRAD)
Table 2-34. DDRAD Field Descriptions
1
DDRAD1
0
0
DDRAD0
0
Field
Description
7–0
Data Direction Port AD — This register configures port pins AD[7:0] as either input or output.
DDRAD[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
PTAD or PTIAD registers, when changing the DDRAD register.
2.3.2.6.4 Port AD Reduced Drive Register (RDRAD)
Module Base + 0x0033
7
R
RDRAD7
W
Reset
0
6
RDRAD6
5
RDRAD5
4
RDRAD4
3
RDRAD3
2
RDRAD2
1
RDRAD1
0
0
0
0
0
0
Figure 2-43. Port AD Reduced Drive Register (RDRAD)
0
RDRAD0
0
Read: Anytime.
Write: Anytime.
Table 2-35. RDRAD Field Descriptions
Field
Description
7–0
Reduced Drive Port AD — This register configures the drive strength of each port AD output pin as either full
RDRAD[7:0] or reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
102
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.23