XRT72L71 Datasheet, PDF (9/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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PIN DESCRIPTION (CONTINUED)
PIN NO.
8
SYMBOL
RLOL
TYPE
I
9
D11
I/O
10
TxFrame
O
11
D10
I/O
12
Req
O
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
DESCRIPTION
Receive Loss of Lock Indicator—from the XRT7300 E3/DS3/STS-1 LIU IC:
This input pin is intended to be connected to the RLOL (Receive Loss of Lock)
output pin of the XRT7300 LIU IC. The user can monitor the state of this pin by
reading the state of Bit 1 (RLOL) within the Line Interface Scan Register
(Address = 0x73). If this input pin is “Low”, then it means that the phase-locked-
loop circuitry, within the XRT7300 is properly locked onto the incoming DS3
data-stream; and is properly recovering clock and data from this DS3 data-
stream. However, if this input pin is “High”, then it means that the phase-
locked-loop circuitry, within the XRT7300 has lost lock with the incoming DS3
data-stream, and is not properly recovering clock and data.
For more information on the operation of the XRT7300 E3/DS3/STS-1 LIU IC,
please consult the "XRT7300 E3/DS3/STS-1 LIU IC" data sheet.
NOTE: If the designer is not using the XRT7300 DS3/E3/STS-1 LIU IC, this
input pin can be used for other purposes.
Bi-Directional Data bus (Microprocessor Interface Section): This pin is
inactive if the Microprocessor Interface block is configured to operate over an
8-bit wide data bus. Please see description for D15, pin 1.
Transmit End of DS3 Frame Indicator:
The function of this pin is same in both Clear Channel and ATM UNI modes of
the XRT72L71. This pin marks the end of each DS3 frame.
ATM UNI Mode
This pin is pulsed for one DS3 clock period when the transmit input interface
is processing the last bit of the given DS3 frame. This just serves as an indica-
tion to terminal equpiment in the ATM UNI mode.
Clear Channel Mode
When the XRT72L71is configured to operate in the “Clear-Channel Framer”
mode, then the Transmit DS3 Framer block will pulse this output pin “High” (for
one bit period) when the “Transmit Payload Data Input Interface” block is pro-
cessing the last bit of a given DS3 frame.
The purpose of this output pin is to alert the Terminal Equipment that it needs
to begin transmission of a new DS3 frame to the XRT72L71 (e.g., to permit
the XRT72L71 to maintain Transmit DS3 framing alignment control over the
Terminal Equipment).
Bi-Directional Data bus (Microprocessor Interface Section): This pin is
inactive if the Microprocessor Interface block is configured to operate over an
8 bit data bus. (Please see description for D15, pin 1)
Receive Equalization Bypass Control Output Pin—(to be connected to
the XRT7300 E3/DS3/STS-1 LIU IC): This output pin is intended to be con-
nected to the Req input pin of the XRT7300 E3/DS3/STS-1 LIU IC. The user can
control the state of this output pin by writing a ‘0’ or ‘1’ to Bit 5 (Req) of the
Line Interface Driver Register (Address = 0x72). If the user commands this
signal to toggle “High” then it will cause the incoming DS3 line signal to “by-
pass” equalization circuitry, within the XRT7300. Conversely, if the user com-
mands this output signal to toggle “Low”, then the incoming DS3 line signal
with be routed through the equalization circuitry. For information on the criteria
that should be used when deciding whether to bypass the equalization cir-
cuitry or not, please consult the “XRT7300 E3/DS3/STS-1 LIU IC” data sheet.
Writing a “1” to Bit 5 of the Line Interface Drive Register (Address = 0x72) will
cause this output pin to toggle “High”. Writing a “0” to this bit-field will cause
this output pin to toggle “Low”.
NOTE: If the designer is not using the XRT7300 E3/DS3/STS-1 LIU IC, then
this output pin can be used for other purposes.
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