XRT72L71 Datasheet, PDF (78/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
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REGISTER 70
BIT
FUNCTION
7-2 Unused
1 POOF Interrupt Status
0 PLOF Interrupt Status
TABLE 71: RX PLCP INTERRUPT STATUS REGISTER
RX PLCP INTERRUPT STATUS REGISTER
HEX ADDRESS: 0X46
TYPE
RO
DEFAULT
0
DESCRIPTION-OPERATION
RUR
0: Indicates that the “Change in POOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in POOF Condition” interrupt has occurred
0
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71is operating in both the
“ATM UNI” and the “PLCP” Modes.
RUR
0: Indicates that the “Change in PLOF Condition” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Change in PLOF Condition” interrupt has occurred
0
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
REGISTER 71
BIT
FUNCTION
TYPE
TABLE 72: FUTURE USE
FUTURE USE
HEX ADDRESS: 0X47
DEFAULT
DESCRIPTION-OPERATION
REGISTER 72
BIT
FUNCTION
7-0 FA1 Error Mask
REGISTER 73
BIT
FUNCTION
7-0 FA2 Error Mask
TABLE 73: TX PLCP FA1 BYTE ERROR MASK REGISTER
TX PLCP FA1 BYTE ERROR MASK REGISTER
HEX ADDRESS: 0X48
TYPE
DEFAULT
DESCRIPTION-OPERATION
The Transmit PLCP Processor block always XORs contents of this register
with the contents of the FA1 byte (within a PLCP frame). This “XORed” value
is then written back into the “FA1” byte field, within each “outbound” PLCP
Frame; prior to transmission. Setting any of these bit-fields to “1” introduces
R/W
0x00 _{error in that specific bit, within each “outbound” FA1 byte.}
Register must be set to 0x00 for normal operation,
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
TABLE 74: TX PLCP FA2 BYTE ERROR MASK REGISTER
TX PLCP FA2 BYTE ERROR MASK REGISTER
HEX ADDRESS: 0X49
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x00
The Transmit PLCP Processor block always XORs contents of this register
with the contents of the FA2 byte (within a PLCP frame). This “XORed” value
is then written back into the “FA1” byte field, within each “outbound” PLCP
Frame; prior to transmission. Setting any of these bit-fields to “1” introduces
error in that specific bit, within each “outbound” FA1 byte.
Register must be set to 0x00 for normal operation,
NOTE: This bit-field is only active if the XRT72L71 is operating in both the
“ATM UNI” and the “PLCP” Modes.
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