XRT72L71 Datasheet, PDF (84/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
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REGISTER 81
BIT
FUNCTION
7-0 Rx Idle Cell Pattern 2
TABLE 82: RX CP IDLE CELL PATTERN HEADER BYTE-2
RX CP IDLE CELL PATTERN HEADER BYTE-2
HEX ADDRESS: 0X51
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x00
This register (along with the “Rx Idle Cell Mask 2” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 2.
NOTES:
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
REGISTER 82
BIT
FUNCTION
7-0 Rx Idle Cell Pattern 3
TABLE 83: RX CP IDLE CELL PATTERN HEADER BYTE-3
RX CP IDLE CELL PATTERN HEADER BYTE-3
HEX ADDRESS: 0X52
TYPE
DEFAULT
DESCRIPTION-OPERATION
This register (along with the “Rx Idle Cell Mask 3” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 3.
NOTES:
R/W
0x00
1. This register should be set to “0x00” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
REGISTER 83
BIT
FUNCTION
7-0 Rx Idle Cell Pattern 4
TABLE 84: RX CP IDLE CELL PATTERN HEADER BYTE-4
RX CP IDLE CELL PATTERN HEADER BYTE-4
HEX ADDRESS: 0X53
TYPE
DEFAULT
DESCRIPTION-OPERATION
This register (along with the “Rx Idle Cell Mask 1” register) permits the user
to specify the “Idle Cell Filtering” criteria for Header Byte 4.
NOTES:
R/W
0x01
1. This register should be set to “0x01” when the Receive Cell Proces-
sor is receiving “ATM Forum” standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the “ATM
UNI” Mode.
80