XRT72L71 Datasheet, PDF (74/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
áç
REGISTER 55
BIT
FUNCTION
7-0 Cell Drop Count Low-byte
TABLE 56: PMON DISCARDED CELL COUNT - LSB
PMON DISCARDED CELL COUNT - LSB
HEX ADDRESS: 0X37
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This Reset-upon-Read register, along with PMON Discarded Cell Count -
MSB” contains the 16 bit value for the total number of cells that have been
discarded since the last read of this register. This register contains the “Low”
byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
REGISTER 56
BIT
FUNCTION
7-0
Tx Idle Cell Count High-
byte
TABLE 57: PMON TRANSMIT IDLE CELL COUNT - MSB
PMON TRANSMIT IDLE CELL COUNT - MSB
HEX ADDRESS: 0X38
TYPE
DEFAULT
DESCRIPTION-OPERATION
RUR
0x00
This Reset-upon-Read register, along with PMON Transmit Idle Cell Count -
LSB contains the 16 bit value for the total number of Idle cells that have been
trnasmitted by the Transmit Cell Processor, since the last read of this regis-
ter. This register contains the “High” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
REGISTER 57
BIT
FUNCTION
7-0
Tx Idle Cell Count Low-
byte
TABLE 58: PMON TRANSMIT IDLE CELL COUNT - LSB
PMON TRANSMIT IDLE CELL COUNT - LSB
HEX ADDRESS: 0X39
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This Reset-upon-Read register, along with PMON Transmit Idle Cell Count -
MSB contains the 16 bit value for the total number of Idle cells that have
been trnasmitted by the Transmit Cell Processor, since the last read of this
register. This register contains the “Low” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
REGISTER 58
BIT
FUNCTION
7-0
Tx Valid Cell Count High-
byte
TABLE 59: PMON TRANSMIT VALID CELL COUNT - MSB
PMON TRANSMIT VALID CELL COUNT - MSB
HEX ADDRESS: 0X3A
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This Reset-upon-Read register, along with PMON Transmit Valid Cell Count -
LSB contains the 16 bit value for the total number of Valid cells that have
been trnasmitted by the Transmit Cell Processor, since the last read of this
register. This register contains the “High” byte value of this 16-bit expres-
sion.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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