XRT72L71 Datasheet, PDF (23/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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PIN DESCRIPTION (CONTINUED)
PIN NO.
119
SYMBOL
TxOH
TYPE
I
120
TxCellTxed
O
121
TxOHClk
O
122
TxOHFrame
O
123
TxUEn
I
124
TxUSoC
I
125
TxUPrty
I
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
DESCRIPTION
Transmit Overhead Input Pin
The Transmit Overhead Data Input Interface accepts the overhead data via
this input pin, and inserts into the "overhead" bit position within the very next
"outbound" DS3 frame. If the "TxOHIns" pin is pulled "High", the Transmit
Overhead Data Input Interface will sample the data at this input pin (TxOH),
on the falling edge of the "TxOHClk" output pin. Conversely, if the "TxOHIns"
pin is pulled "Low", then the Transmit Overhead Data Input Interface will NOT
sample the data at this input pin (TxOH). Consequently, this data will be
ignored.
Transmit Cell Processor—Cell Transmitted Indicator: This output pin
pulses “High” each time the Transmit Cell Processor transmits a cell to the
Transmit PLCP Processor (or Transmit DS3 Framer).
NOTE: This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
Transmit Overhead Clock:
The function of this pin is the same in both Clear Channel and ATM UNI
Modes of the XRT72L71. This pin serves as the clock signal for the external
interface to insert the OH data on the TxOH pin. The user can insert OH data
on the TxOH pin at the rising edge of this clock signal.
Transmit Overhead Framing Pulse:
The function of this pin is same in both Clear Channel and ATM UNI modes of
XRT72L71. When the external interface samples this pin "High" at the rising
edge of TxOHClk, it should provide 'X' bit (first OH bit within DS3 frame) on
the TxOH pin. This signal is "High" for one TxOHClk duration and repeats
once for each DS3 frame.
Transmit UTOPIA Interface Block—Write Enable: This active-”Low” signal,
from the ATM Layer processor enables the data on the Transmit UTOPIA Data
Bus to be written into the TxFIFO on the rising edge of TxUClk. When this sig-
nal is asserted, then the contents of the byte or word that is present, on the
Transmit UTOPIA Data Bus, will be latched into the Transmit UTOPIA Interface
block, on the rising edge of TxUClk.
When this signal is negated, then the Transmit UTOPIA Data bus inputs will be
tri-stated.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
Transmitter—Start of Cell (SoC) Indicator Input: This input pin is driven by
the ATM Layer processor and is used to indicate the start of an ATM cell that is
being transmitted from the ATM layer processor. This input pin must be pulsed
“High” when the first byte (or word) of a new cell is present on the Transmit
UTOPIA Data Bus. This input pin must remain “Low” at all other times.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
Transmit UTOPIA Data Bus—Parity Input: The ATM Layer processor will
apply the parity value of the byte or word which is being applied to the Trans-
mit UTOPIA Data Bus (e.g., TxUData[7:0] or TxUData[15:0]) inputs of the
UNI, respectively. Note: this parity value should be computed based upon the
odd-parity of the data applied at the Transmit UTOPIA Data Bus. The Transmit
UTOPIA Interface block (within the UNI) will independently compute an odd-
parity value of each byte (or word) that it receives from the ATM Layer proces-
sor and will compare it with the logic level of this input pin.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
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