XRT72L71 Datasheet, PDF (68/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
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REGISTER 31
TABLE 32: TX DS3 LAPD STATUS/INTERRUPT REGISTER
TX DS3 LAPD STATUS/INTERRUPT REGISTER
HEX ADDRESS: 0X1F
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-4 Unused
RO
0
3 Tx DL Start
0 to 1 transition configures the LAPD Transmitter to begin its transmission of
the PMDL (or LAPD Message) consisting of the data residing within the
R/W
0
“Transmit LAPD Message” buffer.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
2 Tx DL Busy
0: LAPD Transmitter is NOT currently transmitting a LAPD Message to the
Remote Terminal Equipment; and is not available to transmit a new LAPD
Message.
RO
0
1: LAPD Transmitter is currently transmitting a LAPD Message to the
Remote Terminal Equipment.
NOTE: This bit-field is only active if the XRT72L71 has been config-
ured to support the “C-bit Parity” Framing format.
1 Tx LAPD Interrupt Enable R/W
0: “Completion of Transmission of LAPD Message” Interrupt is disabled.
1: “Completion of Transmission of LAPD Message” Interrupt is enabled. The
XRT72L71 will generate an interrupt, anytime the LAPD Transmitter has
0
completed its transmission of a given LAPD Message.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
0 Tx LAPD Interrupt Status RUR
0: “Completion of Transmission of LAPD Message” interrupt has NOT
occurred since the last read of this register.
1: “Completion of Transmission of LAPD Message” interrupt has occurred
0
since the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
REGISTER 32
BIT
FUNCTION
7-0 LCV Count High byte
TABLE 33: PMON LCV EVENT COUNT REGISTER - MSB
PMON LCV EVENT COUNT REGISTER - MSB
HEX ADDRESS: 0X20
TYPE
DEFAULT
DESCRIPTION-OPERATION
RUR
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - LSB” contains the 16-bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “High” Byte of this 16-bit expression.
NOTE: This register is only active if the “B3ZS Decoder” (within the
XRT72L71) has been enabled.
REGISTER 33
BIT
FUNCTION
7-0 LCV Count Low byte
TABLE 34: PMON LCV EVENT COUNT REGISTER - LSB
PMON LCV EVENT COUNT REGISTER - LSB
HEX ADDRESS: 0X21
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON LCV Event Count Reg-
ister - MSB” contains the 16 bit value for the total number of Line Code Viola-
tions that have been detected since the last read of this register.
This register contains the “Low” Byte of this 16-bit expression.
NOTE: This register is only active if the “B3ZS Decoder” (within the
XRT72L71) has been enabled.
64