XRT72L71 Datasheet, PDF (70/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
áç
REGISTER 39
BIT
FUNCTION
7-0
FEBE Event Count Low-
byte
TABLE 40: PMON FEBE EVENT COUNT REGISTER - LSB
PMON FEBE EVENT COUNT REGISTER - LSB
HEX ADDRESS: 0X27
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON FEBE Event Count
Register - MSB” contains the 16 bit value for the total number of FEBE
events that have been detected since the last read of this register. This reg-
ister contains the “Low” byte value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
support the “C-bit Parity” Framing format.
REGISTER 40
TABLE 41: PMON PLCP BIP-8 ERROR COUNT REGISTER - MSB
PMON PLCP BIP-8 ERROR COUNT REGISTER - MSB
HEX ADDRESS: 0X28
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
PLCP BIP Error Count
High-byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON PLCP BIP-8 Error
Count Register - LSB” contains the 16 bit value for the total number of PLCP
BIP-8 Errors that have been detected since the last read of this register. This
register contains the “High” bye value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
REGISTER 41
TABLE 42: PMON PLCP BIP-8 ERROR COUNT REGISTER - LSB
PMON PLCP BIP-8 ERROR COUNT REGISTER - LSB
HEX ADDRESS: 0X29
BIT
FUNCTION
7-0
PLCP BIP Error Count
Low-byte
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON PLCP BIP-8 Error
Count Register - MSB” contains the 16 bit value for the total number of PLCP
BIP-8 Errors that have been detected since the last read of this register. This
register contains the “Low” bye value of this 16-bit expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
REGISTER 42
TABLE 43: PMON PLCP FRAMING BYTE ERROR COUNT REGISTER - MSB
PMON PLCP FRAMING BYTE ERROR COUNT REGISTER - MSB
HEX ADDRESS: 0X2A
BIT
FUNCTION
TYPE
7-0
PLCP FA Error Count High-
byte
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON PLCP FA Error Count
Register - LSB” contains the 16 bit value for the total number of PLCP Fram-
ing (e.g, FA1 or FA2) byte errors that have been detected since the last read
of this register. This register contains the “High” byte value of this 16-bit
expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
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