XRT72L71 Datasheet, PDF (47/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

áç
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
• Microprocessor interface supports 8 bit wide or 16-
bit wide read/write accesses.
• Supports polled or interrupt-driven environments.
• Supports burst mode “Read and Write” operations
between the “local” microprocessor and the UNI on-
chip registers and RAM locations.
• Includes a “Loss of Clock Signal” protection feature
that terminates “Read/Write” cycles with the local
µP, during a “Loss of Clock signal” event.
PERFORMANCE MONITOR SECTION
Contains numerous on-chip “Read-Only” registers
that allows the user to monitor the overall “health” of
the system.
TEST AND DIAGNOSTIC SECTION
• Supports Line, PLCP, and Cell Loop-back Modes
• Supports Line-Side Testing
• Contains an on-chip Test Cell Generator and an on-
chip Test Cell Receiver
• Test Cell Generator can generate a “continuous”
stream of test cells, or a “one-shot” burst of 1024
test cells.
• The Test Cell Receiver identifies, collects and eval-
uates Test Cells for errors.
• The Test Cell Receiver also reports the occurrence
of errors to the user.
LINE INTERFACE DRIVE AND SCAN SECTION
• Consists of an on-chip “Read/Write” register that
allows the user to control the state of 6 output pins.
Consists of an on-chip “Read-Only” register that al-
lows the user to monitor the state of 3 input pins.
43