XRT72L71 Datasheet, PDF (13/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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PIN DESCRIPTION (CONTINUED)
PIN NO.
35
SYMBOL
WR_RW
TYPE
I
36
RxSerData/
O
RxPOH
37
A8
I
38
RxSerClk/
O
RxPOHClk
39
A7
I
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
DESCRIPTION
Write Data Strobe (Intel Mode): If the microprocessor interface is operating
in the Intel Mode, then this active-”Low” input pin functions as the WR (Write
Strobe) input signal from the µP. Once this active-”Low” signal is asserted,
then the UNI will latch the contents of the µP Data Bus, into the addressed
register (or RAM location) within the UNI/Framer IC.
R/W Input Pin (Motorola Mode): When the Microprocessor Interface Section
is operating in the “Motorola Mode”, then this pin is functionally equivalent to
the “R/W*” pin. In the Motorola Mode, a “READ” operation occurs if this pin is
at a logic “1”. Similarly, a WRITE operation occurs if this pin is at a logic “0”.
Receive Serial Output/Receive PLCP Frame Path Overhead (POH)
Byte Serial Output Port—Output Pin:
The exact functionality of this output pin depends upon whether the
XRT72L71 Framer IC is operating in the Clear Channel or ATM UNI Mode.
Clear Channel Mode:
In clear channel mode, all DS3 data which is received by XRT72L71 will be
output as a serial data stream via this pin. The XRT72L71 will output data (via
this pin) upon the falling edge of “RxSerClk”. As a consequence, this data
should be sampled with the rising edge of RxSerClk.
ATM UNI Mode:
This output pin, along with RxPOHClk, RxPOHFrame, and RxPOHIns pins
comprise the “Receive PLCP Frame POH Byte” serial output port. For each
PLCP frame that is received by the Receive PLCP Processor, this serial out-
put port will output the contents of all 12 POH (Path Overhead) bytes. The
data that is output via this pin, is updated on the rising edge of the RxPOHClk
output clock signal. The RxPOHFrame pin will pulse “High” when the first bit of
the Z6 byte is being output on this output pin.
Address Bus Input (Microprocessor Interface)—MSB (Most Significant
Bit):
This input pin, along with inputs A0 - A7 are used to select the on-chip UNI
register and RAM space for READ/WRITE operations with the “local” micro-
processor.
Clear Channel Mode Receive Clock Output Signal for Serial Data
Interface/ Receive PLCP Frame Path Overhead (POH) Byte Serial Out-
put Port—Output Clock Signal:
The exact functionality of this output pin depends upon whether the
XRT72L71 Framer IC is operating in the Clear Channel or ATM UNI Mode.
Clear Channel Mode - RxSerClk:
In clear channel mode, this pin can be used by the external interface to sam-
ple the clear channel serial data stream on RxSer pin. The Receive Section of
the XRT72L71 will output all “inbound” DS3 data, via the “RxSerData” output
pin, upon the rising edge of this output pin. Hence, the user should be sam-
pling the data (on the “RxSerData” output pin) upon the rising edge of this
clock.
ATM UNI MODE - RxPOHClk:
In the ATM UNI mode of operation, this pin serves as RxPOHClk.
This output clock pin, along with RxPOH, RxPOHframe pins comprise the
'Receive PLCP OH serial output' interface.
Address Bus Input (Microprocessor Interface):
Please see description for A8, pin 37.
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