XRT72L71 Datasheet, PDF (26/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
PIN DESCRIPTION (CONTINUED)
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PIN NO.
156
SYMBOL
TxGFCClk
157
ALE_AS
158
TxGFC
159
GND
160
RDY_DTCK
TYPE
O
I
I
***
O
DESCRIPTION
Transmit GFC Nibble Field Serial Input Port Clock: This signal, along with
TxGFC, and TxGFCMSB combine to function as the “Transmit GFC Nibble-
field” serial input port. The “Transmit GFC Nibble-field” serial input port uses
this output clock signal to sample the values applied to the TxGFC pin, on its
rising edge. This pin will provide four rising edges for each cell being transmit-
ted.
NOTE: This output pin is only active whenever the XRT72L71 has been con-
figured to operate in the “ATM UNI” Mode.
Address Latch Enable/Address Strobe: This input is used to latch the
address (present at the Microprocessor Interface Address Bus, A[8:0]) into the
UNI Microprocessor Interface circuitry and to indicate the start of a READ/
WRITE cycle. This input is active-"High" in the Intel Mode (MOTO = “Low”)
and active-”Low” in the Motorola Mode (MOTO = “High”).
Transmit GFC Nibble-Field Serial Input Port: This signal, along with TxG-
FCClk and TxGFCMSB combine to function as the “Transmit GFC Nibble-
field” serial input port. The user will specify the value of the GFC field, within a
given ATM cell, by serial transmitting its four bit value into this input. Each of
these four bits will be clocked into the UNI via rising edge of the TxGFCClk
clock output signal.
NOTE: The user should tie this input pin to “GND” whenever the XRT72L71
has been configured to operate in the “Clear-Channel-Framer” Mode.
Ground Signal Pin
READY or DTACK: This active-”Low” output pin will function as the READY
output, when the microprocessor interface is running in the “Intel” Mode; and
will function as the DTACK output, when the microprocessor interface is running
in the “Motorola” Mode.
“Intel” Mode—READY Output. When the UNI negates this output pin (e.g.,
toggles it “Low”), it indicates (to the µP) that the current READ or WRITE
cycle is to be extended until this signal is asserted (e.g., toggled “High”).
“Motorola” Mode:—DTACK (Data Transfer Acknowledge) Output. The
UNI Framer will assert this pin in order to inform the local microprocessor that
the present READ or WRITE cycle is nearly complete. If the UNI Framer
requires that the current READ or WRITE cycle be extended, then the UNI will
delay its assertion of this signal. The 68000 family of µPs requires this signal
from its peripheral devices, in order to quickly and properly complete a READ
or WRITE cycle.
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