XRT72L71 Datasheet, PDF (45/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
Signal Name
Function of Output Pin
RLOOP
LLOOP
Remote Loop-Back Mode Select:
This bit-field, along with LLOOP can be used to configure the XRT7300 into one of four different loop-
back modes.
Setting RLOOP to “1” (with LLOOP = 0) configures the XRT7300 to operate in the Remote Loop-Back
Mode.
Setting RLOOP to “1” (with LLOOP = 1) configures the XRT7300 to operate in the “Digital Local Loop-
Back” Mode.
Setting RLOOP to “0” (with LLOOP = 1) configures the XRT7300 to operate in the “Analog Local Loop-
Back” Mode.
Setting RLOOP to “0” (with LLOOP = 0) configures the XRT7300 to operate in the “Normal” (No-Loop-
back) Mode.
Local Loop-Back Mode Select:
This bit-field along with RLOOP can be used to configure the XRT7300 into one of four different loop-
back modes.
Setting LLOOP to “1” (with RLOOP = 0) configures the XRT7300 to operate in the “Analog Local Loop-
Back” Mode.
Setting LLOOP to “1” (with RLOOP = 1) configures the XRT7300 to operate in the “Digital Local Loop-
Back” Mode.
Setting LLOOP to “0” (with RLOOP = 0) configures the XRT7300 to operate in the “Normal” (No-Loop-
Back) Mode.
Setting LLOOP to “0” (with RLOOP = 1) configures the XRT7300 to operate in the “Remote Loop-Back”
Mode.
• The On-Chip Line Interface Scan Register allows
the user to monitor the state of 3 input pins. The
function of these input pins, when asserted, are
tabulated below.
SIGNAL NAME
DMO
RLOL
RLOS
FUNCTION OF INPUT PIN IF ASSERTED
Indicates that the "Drive Monitor" circuitry within the XRT7300 has not detected any bipolar signals
within the last 128 ± 32 bit periods.
Indicates that the "Clock Recovery" circuit, within the XRT7300 has lost "lock" with the incoming DS3
line signal.
Indicates that the XRT7300 is declaring an LOS (Loss of Signal) Condition.
FEATURES
TRANSMIT AND RECEIVE SECTIONS
UTOPIA INTERFACE BLOCKS
• Compliant with UTOPIA Level 2 Interface Specifica-
tion (e.g., supports Single-PHY or Multi-PHY opera-
tion).
• 8-bit or 16-bit wide UTOPIA Data Bus operation in
the Transmit and Receive Directions.
• The UTOPIA Data Bus runs at clock rates of 25
MHz, 33 MHz and 50 MHz
• Supports both Octet-Level and Cell-Level Hand-
shaking between the UNI and the ATM Layer pro-
cessor.
• The Transmit UTOPIA Interface block performs par-
ity checking of ATM cell data that is written into it,
by the ATM Layer processor. Will optionally discard
errored cells.
• Contains on-chip 16 cell FIFO in the Transmit Direc-
tion (TxFIFO)
• The TxFIFO can be configured to operate with
depths of 4, 8, 12 or 16 cells
• Contains on-chip 16 cell FIFO in the Receive
Direction (RxFIFO)
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