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XRT72L71 Datasheet, PDF (83/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER | |||
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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
REGISTER 79
TABLE 80: RX CP INTERRUPT STATUS REGISTER
RX CP INTERRUPT STATUS REGISTER
HEX ADDRESS: 0X4F
BIT
FUNCTION
TYPE
7 OAM Buffer/FIFO Overflow RUR
DEFAULT
DESCRIPTION-OPERATION
0: Receive OAM Cell Buffer/FIFO has not experienced an âOverrunâ event
since the last read of this register.
1: Receive OAM Cell Buffer/FIFO has experienced an âOverrunâ event since
0
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the âATM
UNIâ Mode.
6-3 Unused
RO
0
OAM FIFO mode:
0: Indicates that the âReceive OAM Cell FIFOâ is empty and does not con-
tain any new OAM cell data.
1: Indicates that there at least one unread OAM cell exists within the
âReceive OAM Cell FIFOâ.
2
OAM Interrupt Status/
OAM Cell Pending
RUR/RO
0
NOTE: If the âReceive OAM Cellâ Buffer/FIFO is configured to operate in the
âFIFOâ Mode, then this bit-field is âRead-Onlyâ.
OAM Buffer Mode:
0: Indicates that the âReceipt of OAM Cellâ Interrupt has NOT occurred since
the last read of this register.
1: Indicates that the âReceipt of OAM Cellâ Interrupt has occurred since the
last read of this register.
1 LCD Interrupt Status
RUR
0: Indicates that the âChange in LCD Conditionâ interrupt has NOT occurred
since the last read of this register.
1: Indicates that the âChange in LCD Conditionâ Interrupt has occurred since
0
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the âATM
UNIâ Mode.
0
HEC Byte Error Interrupt
Status
RUR
0: Indicates that the âDetection of HEC Byteâ Error has NOT occurred since
the last read of this register.
1: Indicates that the âDetection of HEC Byteâ Error has occurred since the
0
last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is operating in the âATM
UNIâ Mode.
REGISTER 80
BIT
FUNCTION
7-0 Rx Idle Cell Pattern 1
TABLE 81: RX CP IDLE CELL PATTERN HEADER BYTE-1
RX CP IDLE CELL PATTERN HEADER BYTE-1
HEX ADDRESS: 0X50
TYPE
DEFAULT
DESCRIPTION-OPERATION
This register (along with the âRx Idle Cell Mask 1â register) permits the user
to specify the âIdle Cell Filteringâ criteria for Header Byte 1.
NOTES:
R/W
0x00
1. This register should be set to â0x00â when the Receive Cell Proces-
sor is receiving âATM Forumâ standard Idle Cells.
2. This bit-field is only active if the XRT72L71 is operating in the âATM
UNIâ Mode.
79
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