XRT72L71 Datasheet, PDF (60/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
áç
REGISTER 19
TABLE 20: RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER
HEX ADDRESS: 0X13
BIT
FUNCTION
7-5 Unused
TYPE
RO
DEFAULT
0
DESCRIPTION-OPERATION
4 FEAC Valid
0: Received FEAC code (residing in “RxFEAC[5:0]”) has been “removed”.
1: Received FEAC code (residing in “RxFEAC[5:0]”) has been “validated”.
RO
0
NOTE: This bit-field is only valid if the XRT72L71 is configured to support
the “C-bit Parity” Framing Format.
3
Rx FEAC Remove Interrupt
Enable
R/W
0: RxFEAC Removal Interrupt is disabled.
1: Generates an interrupt upon removal of previously validated FEAC code is
0
enabled
NOTE: This bit-field is only valid if the XRT72L71 is configured to support
the “C-bit Parity” Framing Format.
2
Rx FEAC Remove Interrupt
Status
RUR
0: Indicates that no received FEAC Messages have been removed since the
last read of this register.
1: Indicates that a received FEAC Message has been removed since the last
0
read of this register.
NOTE: This bit-field is only valid if the XRT72L71is configured to support the
“C-bit Parity” Framing Format.
1
Rx FEAC Valid Interrupt
Enable
R/W
0
Rx FEAC Valid Interrupt
Status
RUR
0: RxFEAC Validation Interrupt is disabled.
1: Generates an interrupt upon validation of a newly received FEAC mes-
0
sage.
NOTE: This bit-field is only valid if the XRT72L71 is configured to support
the “C-bit Parity” Framing Format.
0: Indicates that no received FEAC Messages have been validated since the
last read of this register.
1: Indicates that a newly received FEAC Message has been validated since
0
the last read of this register.
NOTE: This bit-field is only valid if the XRT72L71 is configured to support
the C-bit Parity” Framing Format.
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