XRT72L71 Datasheet, PDF (71/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
REGISTER 43
TABLE 44: PMON PLCP FRAMING BYTE ERROR COUNT REGISTER - LSB
PMON PLCP FRAMING BYTE ERROR COUNT REGISTER - LSB
HEX ADDRESS: 0X2B
BIT
FUNCTION
TYPE
7-0
PLCP FA Error Count Low-
byte
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON PLCP FA Error Count
Register - MSB” contains the 16 bit value for the total number of PLCP Fram-
ing (e.g, FA1 or FA2) byte errors that have been detected since the last read
of this register. This register contains the “Low” byte value of this 16-bit
expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
REGISTER 44
TABLE 45: PMON PLCP FEBE COUNT REGISTER - MSB
PMON PLCP FEBE COUNT REGISTER - MSB
HEX ADDRESS: 0X2C
BIT
FUNCTION
7-0
PLCP FEBE Count High-
byte
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON PLCP FEBE Count
Register - LSB” contains the 16 bit value for the total number of PLCP FEBE
(Far-End Block Error) events that have been detected since the last read of
this register. This register contains the “High” byte value of this 16-bit
expression.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
REGISTER 45
BIT
FUNCTION
7-0
PLCP FEBE Count Low-
byte
TABLE 46: PMON PLCP FEBE COUNT REGISTER -LSB
PMON PLCP FEBE COUNT REGISTER -LSB
HEX ADDRESS: 0X2D
TYPE
RUR
DEFAULT
DESCRIPTION-OPERATION
0x00
This “Reset-upon-Read” register, along with “PMON PLCP FEBE Count
Register - MSB” contains the 16 bit value for the total number of PLCP FEBE
(Far-End Block Error) events that have been detected since the last read of
this register. This register contains the “Low” byte value of this 16-bit expres-
sion.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in both the “ATM UNI” and “PLCP” Modes.
REGISTER 46
TABLE 47: PMON SINGLE-BIT HEC ERROR COUNT - MSB
PMON SINGLE-BIT HEC ERROR COUNT - MSB
HEX ADDRESS: 0X2E
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
S-HEC Error Count High-
byte
RUR
0x00
This “Reset-upon-Read” register, along with “PMON Single-Bit HEC Error
Count Register - LSB” contains the 16 bit value for the total number of Sin-
gle-bit HEC byte errors that have been detected since the last read of this
register. This register contains the “High” byte value of this 16-bit expres-
sion.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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