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XRT72L71 Datasheet, PDF (29/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER
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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: TA = 25°C, VDD = 3.3V ± 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
CONDITIONS
t27
TxOH Data Hold time from rising edge
of TxOHClk signal
0
ns
t28
TxOHIns signal setup time to rising
edge of TxOHClk
11
ns
t29
TxOHIns signal hold time from rising
edge of TxOHClk
0
ns
Transmit DS3 Framer (LIU Interface Port)—See Figure 8 and Figure 9
Delay time of data on TxPOS or TxNEG,
t30
following the rising edge of the
0.7
TxLineClk
Transmit DS3 Framer is config-
2.0
ns
ured to update TxPOS and
TxNEG on the rising edge of
TxLineClk.
Delay time of data on TxPOS or
t31
TxNEG following the falling edge
0.7
of the TxLineClk
Transmit DS3 Framer is config-
1.5
ns
ured to update TxPOS and
TxNEG on the falling edge of
TxLineClk.
fTxLineClk Clock frequency of TxLineClk
44.736
MHz
t32
Period of TxLineClk clock signal
10
ns
t33
Bit Period of data on TxPOS or
TxNEG pins
10
ns
Receive DS3 Framer (Serial Output Port)—See Figure 10
fRxOHClk Frequency of RxOHClk signal
526.3
kHz
t34
Period of RxOHClk clock signal
1900
ns
t35
Delay Time from rising edge of
RxOHClk to RxOHFrame signal
950
970 ns >0.5 t34
t36
Delay Time from rising edge of
RxOHClk to valid data at RxOH
950
970 ns >0.5 t34
t37
Bit Period of data at RxOH
1900
ns
Receive DS3 Framer (LIU Interface Port)—See Figure 11 and Figure 12
t38
RxPOS/RxNEG data Setup Time to
rising edge of RxLineClk
6
Receive DS3 Framer is configured
ns to sample RxPOS and RxNEG
on the rising edge of RxLineClk.
t39
RxPOS/RxNEG data Hold Time from
rising edge of RxLineClk
3
Receive DS3 Framer is configured
ns to sample RxPOS and RxNEG
on the rising edge of RxLineClk.
t40
RxPOS/RxNEG data Setup Time to
falling edge of RxLineClk
6
Receive DS3 Framer is configured
ns to sample RxPOS and RxNEG
on the falling edge of RxLineClk.
t41
RxPOS/RxNEG data Hold Time from
falling edge of RxLineClk
3
Receive DS3 Framer is configured
ns to sample RxPOS and RxNEG
on the falling edge of RxLineClk.
fRxLineClk Clock frequency of RxLineClk
44.736
MHz
t42
Period of RxLineClk clock signal
10
ns
25