XRT72L71 Datasheet, PDF (55/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
REGISTER 7
TABLE 8: TEST CELL ERROR ACCUMULATOR HOLDING REGISTER
TEST CELL ERROR ACCUMULATOR HOLDING REGISTER
HEX ADDRESS: 0X07
BIT
FUNCTION
7-0
TEST CELL HOLDING
REGISTER
TYPE
RO
DEFAULT
DESCRIPTION-OPERATION
0x00
Holds the “Unread” byte of the 16-bit Test Cell Error Accumulator, when that
register is read. The XRT72L71 will transfer the contents of the “Unread”
byte to this “Holding” register, anytime the Bidirectional Data Bus (of the
Microprocessor Interface) is configured to be 8-bits wide.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
REGISTER 8
BIT
FUNCTION
7-0
TEST CELL HEADER
BYTE 1
REGISTER 9
BIT
FUNCTION
7-0
TEST CELL HEADER
BYTE 2
REGISTER 10
BIT
FUNCTION
7-0
TEST CELL HEADER
BYTE 3
TABLE 9: TEST CELL HEADER BYTE-1
TEST CELL HEADER BYTE-1
HEX ADDRESS: 0X08
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x11
Test Cell Header Byte - 1
Permits the user to define the value of “Header Byte # 1” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 10: TEST CELL HEADER BYTE-2
TEST CELL HEADER BYTE-2
HEX ADDRESS: 0X09
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x22
Test Cell Header Byte - 2
Permits the user to define the value of “Header Byte # 2” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
TABLE 11: TEST CELL HEADER BYTE-3
TEST CELL HEADER BYTE-3
HEX ADDRESS: 0X0A
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x33
Test Cell Header Byte - 3
Permits the user to define the value of “Header Byte # 3” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
REGISTER 11
BIT
FUNCTION
7-0
TEST CELL HEADER
BYTE 4
TABLE 12: TEST CELL HEADER BYTE-4
TEST CELL HEADER BYTE-4
HEX ADDRESS: 0X0B
TYPE
R/W
DEFAULT
DESCRIPTION-OPERATION
0x44
Test Cell Header Byte - 4
Permits the user to define the value of “Header Byte # 4” within each Test Cell
which is generated by the “Test Cell Generator”.
NOTE: This register is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
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