XRT72L71 Datasheet, PDF (89/102 Pages) Exar Corporation – DS3 ATM UNI/CLEAR CHANNEL FRAMER

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XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
REGISTER 96
TABLE 97: TX CP CONTROL REGISTER
TX CP CONTROL REGISTER
HEX ADDRESS: 0X60
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7 Scrambler Enable
R/W
1
0: Disables scrambling of payload bits
1: Enables scrambling of payload bits
6 Coset Enable
R/W
1
0: Disables addition of Coset Polynomial to HEC byte
1: Enables addition of Coset Polynomial to HEC byte
5
Valid Cell HEC Insert
Enable
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” valid ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
NOTES:
R/W
1
1. This register bit-field only applies to Valid (e.g., User and OAM)
cells.
2. This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” mode.
4 TDP Check Pattern
0: An Alternating 0x55/0xAA pattern is expected (as the “Data Path Integrity
Check byte) in the fifth octet position, within each Valid cell that is processed
by the Transmit Cell Processor.
1: A constant 0x55 pattern is expected (as the “Data Path Integrity Check”
R/W
1
byte) in the fifth octet position, within each Valid cell that is processed by the
Transmit Cell Processor.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
3 GFC Insert Enable
0: The “GFC Input Port” is disabled.
1: The “GFC Input Port” is enabled. Data is read via TxGFC serial input pin
R/W
0
and is inserted into GFC nibble-field within of each “outbound” ATM cell.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
2 TDP Error Interrupt Enable R/w
0
0: Disables the “Data Path Integrity Check” interrupt.
1: Enables the “Data Path Integrity Check” interrupt.
1 Idle Cell HEC Insert Enable R/w
0: HEC Byte Calculation and Insertion is disabled. Hence, no modification is
performed on the 5th octet within each “outbound” Idle ATM cell.
1: HEC Byte Calculation and Insertion are enabled.
1
NOTES:
1. This register bit-field only applies to Idle cells.
2. This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” mode.
0 TDP Error Interrupt Status RUR
0: Indicates that the “Data Path Integrity Check” Interrupt has not occurred
since the last read of this register.
1: Indicates that the “Data Path Integrity Check” Interrupt has occurred since
0
the last read of this register.
NOTE: This bit-field is only active if the XRT72L71 is configured to
operate in the “ATM UNI” Mode.
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