Z380 Datasheet, PDF (99/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
Standby Mode Entering Timing
Figure 53 shows standby mode entering timing in an
example where IOCLK was programmed to be BUSCLK
divided-by-2. Note that clocking stops only after IOCLK
has changed to logic 0.
BUSCLK
IOCLK
/STNBY
ADDRESS
DATA
BUS
CNTLS
FFFFFFFFH
Figure 53. Standby Mode Entering Timing
(/TREFR, /TREFA, /TREFC,
/MRD, /MWR, /BHEN,
/BLEN, /IOCTL3-0)
Standby Mode Exit With Reset
When /RESET is asserted, /STNBY goes to logic 1, allowing
the external crystal oscillator that drives the Z380 MPU’s
CLKI input to restart. The /RESET pulse provided should
be of a duration long enough for oscillator stabilization. The
Z380 MPU exits standby mode, and when /RESET is
deasserted, it goes through the normal reset timing to start
instruction execution at address 00000000H. Note that
clocking resumes within the Z380 MPU and at the BUSCLK
and IOCLK outputs soon after /RESET is asserted, when
the crystal oscillator is not yet stabilized.
BUSCLK
OPCODE
FETCH
IOCLK
/STNBY
/RESET
ADDRESS
FFFFFFFFH
000000H
DATA
Figure 54. Standby Mode Exit with Reset Timing
PS010001-0301