Z380 Datasheet, PDF (45/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
DATA TYPES
MICROPROCESSOR
The Z380 CPU can operate on bits, Binary-Coded Decimal
(BCD) digits (4 bits), bytes (8 bits), words (16 bits or
32 bits), byte strings, and word strings. Bits in registers can
be set, cleared, and tested. BCD digits, packed two to a
byte, can be manipulated with the Decimal Adjust Accu-
mulator instruction (in conjunction with binary addition and
subtraction) and the Rotate Digit instructions. Bytes are
operated on by 8-bit load, arithmetic, logical, and shift and
rotate instructions. Words are operated on in a similar
manner by the word load, arithmetic, logical, and shift and
rotate instructions. Block move and search operations can
manipulate byte strings and word strings up to 64 Kbytes
or words long. Block I/O instructions have identical capa-
bilities.
CPU Registers
The Z380 CPU contains abundant register resources (Fig-
ure 21). At any given time, the program has immediate
access to both the primary and alternate registers in the
selected register set. Changing register sets is a simple
matter of a LDCTL instruction.
Primary and Working Registers
The working register set is divided into the two register
files; the primary file and the alternate (designated by ‘) file.
Each file contains an 8-bit Accumulator (A), a Flag register
(F), and six general-purpose registers (B, C, D, E, H, and
L). Only one file can be active at any given time, although
data in the inactive file can still be accessed. Upon reset,
the primary register file in register set 0 is active. Exchange
instructions allow the programmer to exchange the active
file with the inactive file.
The accumulator is the destination register for 8-bit arith-
metic and logical operations. The six general-purpose
registers can be paired (BC, DE, and HL), and are
extended to 32 bits by the z extension to the register, to
form three 32-bit general-purpose registers. The HL regis-
ter serves as the 16-bit or 32-bit accumulator for word
operations.
CPU Flag Register
The Flag register contains six flags that are set or reset by
various CPU operations. This register is illustrated in Fig-
ure 24 and the various flags are described below.
S Z X H X P/V N C
76543210
Carry (C). This flag is set when an add instruction gener-
ates a carry or a subtract instruction generates a borrow.
Certain logical, rotate and shift instructions affect the Carry
flag.
Add/Subtract (N). This flag is used by the Decimal Adjust
Accumulator instruction to distinguish between add and
subtract operations. The flag is set for subtract operations
and cleared for add operations.
Parity/Overflow (P/V). During arithmetic operations this
flag is set to indicate a two’s complement overflow. During
logical and rotate operations, this flag is set to indicate
even parity of the result or cleared to indicate odd parity.
Half Carry (H). This flag is set if an 8-bit arithmetic
operation generates a carry or borrow between bits 3 and
4, or if a 16-bit operation generates a carry or borrow
between bits 11 and 12, or if a 32-bit operation generates
a carry or borrow between bits 27 and 28. This bit is used
to correct the result of a packed BCD addition or subtract
operation.
Zero (Z). This flag is set if the result of an arithmetic or
logical operation is a zero.
Sign (S). This flag stores the state of the most significant bit
of the accumulator.
Index Registers
The four index registers, IX, IX’, IY and IY’, each hold a
32-bit base address that is used in the Indexed addressing
mode. The Index registers can also function as general-
purpose registers with the upper and lower byte of the
lower 16 bits being accessed individually. These byte
registers are called IXU, IXU’, IXL and IXL’ for the IX and IX’
registers, and IYU, IYU’, IYL and IYL’ for the IY and IY’
registers.
Interrupt Register
The Interrupt register (I) is used in interrupt modes 2 and
3 for /INT0 to generate a 32-bit indirect address to an
interrupt service routine. The I register supplies the upper
twenty-four or sixteen bits of the indirect address and the
interrupting peripheral supplies the lower eight or sixteen
bits. In the Assigned Vectors mode for /INT1-3 the upper
sixteen bits of the vector are supplied by the I register; bits
15-9 are the assigned vector base and bits 8-0 are the
assigned vector unique to each of /INT1-3.
Figure 24. CPU Flag Register
PS010001-0301