Z380 Datasheet, PDF (81/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
Interrupt Enable Register
IE3-IE0 (Interrupt Request Enable Flags). These flags
individually indicate F /INT3, /INT2, /INT1 or /INT0 is
enabled. Note that these flags are conditioned with enable
and disable interrupt instructions (with arguments).
MICROPROCESSOR
Reserved bits 7-4. Read as 0s, should write to as 0s.
IER: 00000017H
Read Only
7
-- -- --
000
0
-- IE3 IE2 IE1 IE0
0000
1 _{Reset Value}
Encoded Interrupt
Requests
Interrupt Requests
Enable
Figure 25. Interrupt Enable Register
Assigned Vectors Base Register
AB15-AB9 (Assigned Vectors Base). The Interrupt Regis-
ter Extension, Iz, together with AB15-AB9, define the base
address of the assigned interrupt vectors table in memory
space (Figure 26).
Reserved Bit 0. Read as 0, should write to as 0.
AVBR: 00000018H
R/W
7
0
AB15 AB14 AB13 AB12 AB11 AB10 AB9 --
0000000
0 _{Reset Value}
Reserved
Program as 0
Read as 0
Assigned Vectors
Base
Figure 26. Assigned Vectors Base Register
PS010001-0301