Z380 Datasheet, PDF (43/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
Memory Address Space
The memory address space can be viewed as a string of
4 Gbyte numbered consecutively in ascending order. The
8-bit byte is the basic addressable element in the Z380
MPU memory address space. However, there are other
addressable data elements; bits, 2-byte words, byte strings,
and 4-byte words.
The size of the data element being addressed depends on
the instruction being executed as well as the Word/Long
Word mode. A bit can be addressed by specifying a byte,
and a bit within that byte. Bits are numbered from right to
left, with the least significant bit being bit 0 (Figure 23).
MICROPROCESSOR
The address of a multiple-byte entity is the same as the
address of the byte with the lowest memory address in
the entity. Multiple-byte entities can be stored beginning
with either even or odd memory addresses. A word (either
2-byte or 4-byte entity) is aligned if its address is even;
otherwise, it is unaligned. Multiple bus transactions, which
may be required to access multiple-byte entities, can be
minimized if alignment is maintained.
The formats of multiple-byte data types are also shown in
Figure 23. Note that when a word is stored in memory, the
least significant byte precedes the more significant byte of
the word, as in the Z80 CPU architecture. Also, the lower-
addressed byte is present on the upper byte of the external
data bus.
Bits within a byte:
76543210
16-bit word at address n:
Least Significant Byte
Most Significant Byte
Address n
Address n+1
32-bit word at address n:
D7-0 (Least Significant Byte)
D15-8
D23-16
D31-24 (Most Significant Byte)
Address n
Address n+1
Address n+2
Address n+3
Memory addresses:
Even address (A0=0)
Odd address (A0=1)
Least Significant Byte
Most Significant Byte
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 23. Bit/Byte Ordering Conventions
PS010001-0301