Z380 Datasheet, PDF (94/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
Memory Chip Selects and Waits Master
Control
The memory chip selects and their associated waits are
enabled or disabled by writing to a single register de-
scribed in the following:
MICROPROCESSOR
Memory Selects Master Enable Register
A user can set or reset the desired bits 7-4 in this register
without modifying the states of the remaining bits, with the
SR bit defining the set or reset function.
MSMER: 00000010H
R/W
7
0
ENLM ENUM ENM1 ENM2 -- -- ^-- SR
1 1 0 0 0 0 0 0 <- Reset Value
Set Reset Control
Reser ved
Enable Mid-range Memory Chip
Select Scheme 2 and Waits
Enable Mid-range Memory Chip
Select Scheme 1 and Waits
Enable Upper Memory Chip
Select and Waits
Enable Lower Memory Chip
Select and Waits
Figure 46. Memory Selects Master Enable Register
ENLM (Enable Lower Memory Chip Select and Waits). This
bit at logic 1 enables the /LMCS signal to go active starting
at T1 cycle time of a memory transaction accessing the
lower memory area. The associated programmed wait
states are automatically inserted in the transaction.
ENUM (Enable Upper Memory Chip Select and Waits).
This bit at logic 1 enables the /UMCS signal to go active
starting at T1 cycle time of a memory transaction access-
ing the upper memory area. The associated programmed
wait states are automatically inserted in the transaction.
ENM1 (Enable Mid-range Memory Chip Select Scheme 1
and Waits). This bit at logic 1 enables one of /MCS3-
/MCS0 to go active starting at T1 cycle time of a memory
transaction, depending on which of the mid-range memory
areas 3-0 is being accessed. The corresponding pro-
grammed wait states are automatically inserted in the
transaction.
ENM2 (Enable Mid-range Memory Chip Select Scheme 2
and Waits). This bit at logic 1 enables the /MCS0 to go
active starting at T1 cycle time of a memory transaction
accessing the mid-range memory area. The correspond-
ing programmed wait states are automatically inserted in
the transaction.
Reserved bits 3-1. Read as 0s, should write to as 0s.
SR (Set Reset Control). When writing to the Memory
Selects Master Enable Register with SR = 1, bits 7-4
that are selected with logic 1s are set. When writing with
SR = 0, bits 7-4 that are selected with logic 1s are cleared.
In either case, the bits not selected are not modified. The
SR bit is always read as a logic 0.
Additional Comments. In either chip select scheme, if the
chip select and waits functions are enabled, or their
memory areas are defined to cause overlaps, the prece-
dence of conflict resolution is /LMCS, then /UMCS, then
/MCS3-/MCS0. As an example, consider the case where
both the lower and mid-range memory area 0 are defined
to occupy the same address space. With ENLM = 1 in
the Memory Selects Master Enable Register (ENM1 can
be either 0 or 1), /LMCS goes active in the memory
transaction that accesses the overlapped address space.
With ENLM = 0 and ENM1 = 1, /MCS0 would go active in
the transaction instead. Regardless of the state of
the address bus, the chip select signals are at their inac-
tive logic 1s when the corresponding enable bits in the
Memory Selects Master Enable Register (MSMER) are at
logic 0s, except during DRAM refresh transactions if so
enabled, or the Z380 MPUs CPU is in its halt state, except
during DRAM refresh transactions if so enabled, or the
Z380 MPU relinquishes the system bus with its /BREQ
input active, or the Z380 MPU is in the low power standby
mode.
PS010001-0301