Z380 Datasheet, PDF (44/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
CPU ARCHITECTURE (Continued)
External I/O Address Space
External I/O addresses are generated by I/O instructions,
except those reserved for on-chip I/O address space
accesses, and can take a variety of forms (Table 2). An
I/O read or write is always one transaction, regardless of
the bus size and the type of I/O instruction.
On-chip I/O Address Space
The Z380 MPU's on-chip peripheral functions and a por-
tion of its interrupt functions are controlled by several
on-chip registers, which occupy an On-chip I/O Address
Space. This on-chip I/O address space can be accessed
only with the following reserved on-chip I/O instructions.
MICROPROCESSOR
IN0
IN0
OUT0
TSTIO
R, (n)
(n)
(n), R
n
OTIM
OTIMR
OTDM
OTDMR
When one of these I/O instructions is executed, the Z380
MPU outputs the register address being accessed in a
pseudo transaction of two BUSCLK cycles duration, with
the address signals A31-A8 all at zeros. In the pseudo
transaction, all bus control signals are at their inactive
states.
I/O Instruction
IN A, (n)
IN dst,(C)
IN0 dst,(n)
INA(W) dst,(mn)
DDIR IB INA(W) dst,(lmn)
DDIR IW INA(W) dst,(klmn)
Block Input
OUT (n),A
OUT (C),dst
OUT0 (n),dst
OUTA(W) (mn),dst
DDIR IB OUTA(W) (lmn),dst
DDIR IW OUTA(W) (klmn),dst
Block output
Table 2. External I/O Addressing Options
A31-A24
Address Bus
A23-A16
A15-A8
00000000
BC31-BC24
00000000
00000000
00000000
k
BC31-BC24
00000000
BC31-BC24
00000000
00000000
00000000
k
BC31-BC24
00000000
BC23-BC16
00000000
00000000
l
l
BC23-BC16
00000000
BC23-BC16
00000000
00000000
l
l
BC23-BC16
Contents of A reg
BC15-BC8
00000000
m
m
m
BC15-BC8
Contents of A reg
BC15-BC8
00000000
m
m
m
BC15-BC8
A7-A0
n
BC7-BC0
n
n
n
n
BC7-BC0
n
BC7-BC0
n
n
n
n
BC7-BC0
PS010001-0301