Z380 Datasheet, PDF (46/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
DATA TYPES
Program Counter
The Program Counter (PC) is used to sequence through
instructions in the currently executing program and to
generate relative addresses. The PC contains the 32-bit
address of the current instruction being fetched from
memory. In the Native mode, the PC is effectively only 16
bits long, as carries from bit 15 to bit 16 are inhibited in this
mode. In Extended mode, the PC is allowed to increment
across all 32 bits.
R Register
The R register can be used as a general-purpose 8-bit
read/write register. The R register is not associated with
the refresh controller and its contents are changed only by
the user.
MICROPROCESSOR
Stack Pointer
The Stack Pointer (SP) is used for saving information when
an interrupt or trap occurs and for supporting subroutine
calls and returns. Stack Pointer relative addressing allows
parameter passing using the SP.
Select Register
The Select Register (SR) controls the register set selection
and the operating modes of the Z380 CPU. The reserved
bits in the SR are for future expansion; they will always read
as zeros and should be written with zeros for future
compatibility. The SR is shown in Figure 22.
Addressing Modes
Addressing modes are used by the Z380 CPU to calculate
the effective address of an operand needed for execution
of an instruction. Seven addressing modes are supported
by the Z380 CPU. Of these seven, one is an addition to the
Z80 CPU addressing modes (Stack Pointer Relative) and
the remaining six modes are either existing or extensions
to the Z80 CPU addressing modes.
Register. The operand is one of the 8-bit registers (A, B, C,
D, E, H, L, IXU, IXL, IYU, IYL, A', B', C', D', E', H' or L'); or
is one of the 16-bit or 32-bit registers (BC, DE, HL, IX, IY,
BC', DE', HL', IX', IY' or SP) or one of the special registers
(I or R).
Immediate. The operand is in the instruction itself and has
no effective address. The DDIR IB and DDIR IW decoder
directives allow specification of 24-bit and 32-bit immedi-
ate operands, respectively.
Indirect Register. The contents of a register specify the
effective address of an operand. The HL register is the
primary register used for memory accesses, but BC and
DE can also be used. (For the JP instruction, IX and IY can
also be used for indirection.) The BC register is used for
I/O space accesses.
Direct Address. The effective address of the operand
is the location whose address is contained in the instruc-
tion. Depending on the instruction, the operand is either
in the I/O or memory address space. Sixteen bits of direct
address is the norm, but the DDIR IB and DDIR IW decoder
directives allow 24-bit and 32-bit direct addresses,
respectively.
Indexed. The effective address of the operand is the
location computed by adding the two's-complement signed
displacement contained in the instruction to the contents
of the IX or IY register. Eight bits of index is the norm, but
the DDIR IB and DDIR IW decoder directives allow 16-bit
and 24-bit indexes, respectively.
Program Counter Relative. An 8-, 16- or 24-bit displace-
ment contained in the instruction is added to the Program
Counter to generate the effective address. This mode is
available only for Jump and Call instructions.
Stack Pointer Relative. The effective address of the
operand is the location computed by adding the two's-
complement signed displacement contained in the in-
struction to the contents of the Stack Pointer. Eight bits of
index is the norm, but the DDIR IB and DDIR IW decoder
directives allow 16- and 24-bit indexes, respectively.
PS010001-0301