Z380 Datasheet, PDF (96/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
Refresh Register 2
RFEN (Refresh Enable). Enables the refresh function when
programmed to logic 1.
Refresh Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in refresh transactions.
Reserved bit 6. Read as 0, should write to as 0.
BS5-BS0 (Burst Size). This field defines the number of
refresh transactions per refresh request made to the Z380
MPU's External Interface Logic. The burst size ranges from
1 to 64, with the highest size specified with BS5-BS0 equal
to 0s.
RFSHR2: 00000015H
R/W
7
0
RFEN -- BS5 BS4 BS3 BS2 BS1 BS0
0 0 0 0 0 0 0 0 <- Reset Value
Burst Size
Reser ved
Refresh Enable
T1W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in refresh transactions.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in refresh transactions.
Note that care should be exercised in defining refresh
burst size and request intervals to avoid over-burdening
the system bus with refresh transactions. The memory chip
select signals can be selectively enabled to go active
during refresh transactions, such enabling is described in
the Memory Chip Selects and Waits section.
RFWR: 0000000FH
R/W
7
0
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1 1 1 1 1 1 1 1 <- Reset Value
Figure 49. Refresh Register 2
T3 Waits
T2 Waits
T1 Waits
Figure 50. Refresh Waits Register
PS010001-0301