Z380 Datasheet, PDF (22/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
EXTERNAL INTERFACE (Continued)
MICROPROCESSOR
The Z380 MPU is unique in that it employs separate control
signals for accessing the memory and I/O. This allows the
two interfaces to be optimized independent of one an-
other. The I/O bus control signals allow direct connection
to members of the Z80 family of peripherals of the Z8500
family of peripherals.
All I/O transactions are four IOCLK cycles long unless
extended by Wait states. Wait states may be inserted
between the third and fourth IOCLK cycles in an I/O
transaction and are one IOCLK cycle per wait state. The
external /WAIT input is sampled only after internally-gener-
ated wait states are inserted.
Note that because all I/O bus transactions start on a rising
edge of IOCLK, there may be up to n BUSCLK cycles of
latency between the execution unit request for the transac-
tion and the transaction actually starting, where n is the
programmed clock divisor for IOCLK. This implies that the
lowest possible divisor should always be used for IOCLK.
I/O Read transactions are shown with and without a wait
state (Figures 8A-B). The contents of the data bus is
latched immediately before the falling edge of IOCLK
during the last IOCLK cycle of the transaction.
IOCLK
ADDRESS
DATA
/WAIT
/MI
/IORQ
/IORD
/IOWR
/INTAK
Figure 8A. I/O Read Cycle, No Waits
PS010001-0301