Z380 Datasheet, PDF (84/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
Assigned Interrupt Vectors Mode For
Maskable interrupt INT3-/INT1
When the Z380 MPU recognizes one of the external
maskable interrupts it generates an Interrupt Acknowl-
edge transaction which is different than that for /INT0. The
Interrupt Acknowledge transaction for /INT3-/INT1 has the
I/O bus signal /INTAK active, with /MI, /IORQ, /IORD and/
IOWR inactive. The interrupted PC value is PUSHed onto
the stack. IEF1 and IEF2 are reset to logic 0s, disabling
further maskable interrupt requests. The starting address
of an interrupt service routine is fetched from a table entry
and loaded into the PC to resume execution. The address
of the table entry is composed of the I Extend contents as
A31-A16, the AB bits of the Assigned Vectors Base Reg-
ister as A15-A9 and an assigned interrupt vector specific
to the request being recognized as A8-A0. The assigned
vectors are defined in Table 5.
Table 5. Assigned Interrupt Vectors
Interrupt Source
Assigned Interrupt Vector
/INT1
00H
/INT2
04H
/INT3
08H
MICROPROCESSOR
RETI Instruction
The Z80 family I/O devices are designed to monitor the
Return from Interrupt opcodes in the instruction stream
(RETI-EDH, 4DH), signifying the end of the current inter-
rupt service routine. When detected, the daisy chain within
and among the device(s) resolves and the appropriate
interrupt-under-service condition clears. The Z380 MPU
reproduces the opcode fetch transactions on the I/O bus
when the RETI instruction is executed. Note that the Z380
MPU outputs the RETI opcodes onto both portions of the
data bus (D15-D8 and D7-D0) in the transactions.
PS010001-0301