Z380 Datasheet, PDF (79/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
INTERRUPTS
MICROPROCESSOR
The Z380 MPU’s interrupt structure provides compatibility
with the existing Z80 and Z180 MPUs with the following
exception: The undefined opcode trap’s occurrence is
with respect to the Z380 instruction set, and its response
is improved (vs the Z180) to make trap handling easier.
The Z380 MPU also offers additional features to enhance
flexibility in system design.
Of the five external interrupt inputs provided, the /NMI is a
nonmaskable interrupt. The remaining inputs, /INT3-/INT0,
are four asynchronous maskable interrupt requests.
In an Interrupt Acknowledge transaction, address outputs
A31-A0 are driven to logic 1's. One output among A3-A0 is
driven to logic 0 to indicate the maskable interrupt request
being acknowledged. If /INT0 is being acknowledged,
A3-A1, is at logic 1's and A0 is at logic 0.
Interrupt modes 0 through 3 are supported for the external
maskable interrupt request /INT0. Modes 0, 1 and 2 have
the same schemes as those in the Z80 and Z180 MPUs.
Mode 3 is similar to mode 2, except that 16-bit interrupt
vectors are expected from the I/O devices. Note that 8-bit
and 16-bit I/O devices can be intermixed in this mode by
having external pull up resistors at the data bus signals
D15-D8, for example.
The external maskable interrupt requests /INT3-/INT1 are
handled in an assigned interrupt vectors mode.
As discussed in the CPU Architecture section, the Z380
MPU can operate in either the Native or Extended Mode.
In Native Mode, PUSHing and POPing of the stack to save
and retrieve interrupted PC values in interrupt handling are
done in 16-bit sizes, and the stack pointer rolls over at the
64 Kbyte boundary. In Extended Mode, the PC PUSHes
and POPs are done in 32-bit sizes, and the stack pointer
rolls over at the 4 Gbyte memory space boundary. The
Z380 MPU provides an Interrupt Register Extension, whose
contents are always outputted as the address bus signals
A31-A16 when fetching the starting addresses of service
routines from memory in interrupt modes 2, 3 and the
assigned vectors mode. In Native Mode, such fetches are
automatically done in 16-bit sizes and in Extended Mode,
in 32-bit sizes. These starting addresses should be even-
aligned in memory locations. That is, their least significant
bytes should have addresses with A0 = 0.
Interrupt Priority Ranking
The Z380 MPU assigns a fixed priority ranking to handle its
interrupt sources, as shown in Table 2.
Table 2. Interrupt Priority Ranking
Priority
Interrupt Sources
Highest
↓
Lowest
Trap (undefined opcode)
/NMI
/INT0
/INT1
/INT2
/INT3
PS010001-0301