Z380 Datasheet, PDF (105/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
AC CHARACTERISTICS
Z380^™ Version
No. Symbol
Parameter
1 TcC
2 TwCh
3 TwCl
4 TrC
5 TfC
CLK Cycle Time
CLK Width High
CLK Width Low
CLK Rise Time
CLK Fall Time
6 TdCf(BCr)
7 TdCr(BCf)
8 TdBCr(OUT)
9 TdBCf(OUT)
10 TsIN(BCr)
11 ThIN(BCr)
CLK Fall to BUSCLK Rise Delay
CLK Rise to BUSCLK Fall Delay
BUSCLK Rise to Output Valid Delay
BUSCLK Fall to Output Valid Delay
Input to BUSCLK Rise Setup Time
Input to BUSCLK Rise Hold Time
12 TsBR(BCf)
13 ThBR(BCf)
14 TsMW(BCr)
15 ThMW(BCr)
16 TsMW(BCf)
17 ThMW(BCf)
/BREQ to BUSCLK Fall Setup Time
/BREQ to BUSCLK Fall Hold Time
Mem Wait to BUSCLK Rise Setup Time
Mem Wait to BUSCLK Rise Hold Time
Mem Wait to BUSCLK Fall Setup Time
Mem Wait to BUSCLK Fall Hold Time
18 TsIOW(BCr)
19 ThIOW(BCr)
20 TsIOW(BCf)
21 ThIOW(BCf)
IO Wait to BUSCLK Rise Setup Time
IO Wait to BUSCLK Rise Hold Time
IO Wait to BUSCLK Fall Setup Time
IO Wait to BUSCLK Fall Hold Time
22 TwNMI1
23 TwRES1
24 Tx01(02)
25 Tx01(03)
/NMI Low Width
Reset Low Width
Output Skew (Same Clock Edge)
Output Skew (Opposite Clock Edge)
Notes:
1. Applicable for Data Bus and /MSIZE inputs
2. /BREQ can also be asserted/deasserted asynchronously
3. External waits asserted at /WAIT input
4. Tx01(02) = [Output 1] TdBCr(OUT) - [Output 2] TdBCr(OUT)
or [Output 1] TdBCf(OUT) - [Output 2] TdBCf(OUT)
5. Tx01(03) = [Output 1] TdBCr(OUT) - [Output 3] TdBCf(OUT)
or [Output 1] TdBCf(OUT) - [Output 3] TdBCr(OUT)
Z8038018
Min
Max
55
24.5
24.5
3
3
30
27
6.5
6.5
16
0
16
0
16
0
24
0
24
0
24
0
25
10
–2
+2
–3
+3
MICROPROCESSOR
Note
1
1
2
2
3
3
3
3
3
3
3
3
4
5
PS010001-0301