Z380 Datasheet, PDF (73/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
Mnemonic
RETN
RST p
Symbolic
Operation
Return from NMI
(SP-1) ← PCh
(SP-2) ← PCl
SP ← SP-2
PCh ← 0
PCl ← p
Flags
P/
SZ x Hx VNC
••x•x•••
••x•x•••
Opcode
# of Execute
76 543 210 HEX Bytes Time Notes
11 101 101 ED 2
01 000 101 45
11 t 111
1
2+r N,X4,(10)
4+w N,X3,X5
cc Condition
000 NZ (Non-zero)
001 Z (Zero)
010 NC (Non-carry)
011 C (Carry)
100 PO (Parity Odd), or NV (Non-Overflow)
101 PE (Parity Even), or V (Overflow)
110 P (Sign positive), or NS (No sign)
111 M (Sign negative), or S (Sign)
t
p
000
00H
001
08H
010
10H
011
18H
100
20H
101
28H
110
30H
111
38H
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I:
N:
X3:
X4:
X5:
(2)
(8):
(9):
(10)
(11):
This instruction may be used with DDIR Immediate instructions.
In Native mode, this instruction uses addresses modulo 65536.
In Extended mode, this instruction pushes PC(31-16) into the stack before pushing PC(15-0) into the stack.
In Extended mode, this instruction pops PC(31-16) from the stack after poping PC(15-0) from the stack.
In Extended mode, this instruction loads 00h into PC(31-16).
In Extended mode, all return instructions pops PCz from the stack after poping PC from the stack.
ee is a signed two’s complement number in the range [-32765, 32770], ee-4 in the opcode provides an effective address of pc+e as PC is
incremented by 4 prior to the addition of e.
eee is a signed two’s complement number in the range [-8388604, 8388611], eee-5 in the opcode provides an effective address of pc+e as
PC is incremented by 5 prior to the addition of e.
RETN loads IFF2 to IFF1.
e is a signed two’s complement number in the range [-127, 128], e-3 in the opcode provides an effective address of pc+e as PC is incremented
by 3 prior to the addition of e.
PS010001-0301