Z380 Datasheet, PDF (86/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
I/O Bus Control Register 1
When this phantom register IOCR1 with address
00000012H is accessed with one of the on-chip I/O write
instructions, a heartbeat transaction that emulates a Z80
CPU instruction fetch is performed on the I/O bus. This
transaction provides a /M1 pulse which is necessary as
part of an interrupt enable sequence for a Z80 PIO product.
In the on-chip I/O write instruction, the data being "written"
can be of any value. In case of an on-chip I/O read with the
IOCR1 address, the data returned is unpredictable.
I/O Waits Register
OW2-IOW0 (I/O Waits). This binary field defines up to
seven wait states to be inserted in external I/O read and
write transactions, and at the latter portions of interrupt
transactions to capture interrupt vectors. The defined wait
MICROPROCESSOR
states are also inserted in each of the opcode fetch
transactions of the Return from Interrupt (RETI) instruction
reproduced on the I/O bus. When programmed with 0s, the
I/O waits are disabled.
RTW1-RTW0 (RETI Waits). This binary field defines up to
three wait states to be inserted between opcode fetch
transactions of the Return from Interrupt instruction repro-
duced on the I/O bus.
DCW2-DCW0 (Interrupt Daisy Chain Waits). This binary
field defines up to seven wait states to be inserted at the
early portions of interrupt acknowledge transactions, for
the interrupt daisy chain through the external I/O devices
to settle.
IOWR: 0000000EH
R/W
7
0
IOW2 IOW1 IOW0 RTW1 RTW0 DCW2 DCW1 DCW0
1 1 1 1 1 1 1 1 <- Reset Value
Interrupt Daisy
Chain Waits
RET I Waits
I/O Waits
Figure 29. I/O Waits Register
PS010001-0301