Z380 Datasheet, PDF (78/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
16-BIT INPUT AND OUTPUT GROUP (Continued)
MICROPROCESSOR
Mnemonic
OUTDW
OTDRW
Symbolic
Operation
BC(15-0) ← BC(15-0) - 1
(DE) ← (HL)
HL ← HL - 2
BC(15-0) ← BC(15-0) - 1
(DE) ← (HL)
HL ← HL - 2
Repeat until B = 0
Flags
P/
SZ x Hx VNC
• ¤ x • x • 1•
(1)
Opcode
# of Execute
76 543 210 HEX Bytes Time Notes
11 101 101 ED
11 101 011 EB
2 2+r+o
• 1 x • x • 1 • 11 101 101 ED
(2)
11 111 011 FB
2 2+r+o
ppp
Reg
000
BC
010
DE
111
HL
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
I: This instruction may be used with DDIR Immediate instructions.
N: In Native mode, this instruction uses addresses modulo 65536.
(1) If the result of B-1 is zero, the Z flag is set; otherwise it is reset.
(2) Z flag is set upon instruction completion only.
I/O Instruction
IN A, (n)
IN dst,(C)
INA(W) dst,(mn)
DDIR IB INA(W) dst,(lmn)
DDIR IW INA(W) dst,(klmn)
Block Input
OUT (n),A
OUT (C),dst
OUTA(W) (mn),dst
DDIR IB OUTA(W) (lmn),dst
DDIR IW OUTA(W) (klmn),dst
Block output
A31-A24
00000000
BC31-BC24
00000000
00000000
k
BBC31-BC24
00000000
BC31-BC24
00000000
00000000
k
BC31-BC24
Address Bus
A23-A16
A15-A8
00000000
BC23-BC16
00000000
l
l
BC23-BC16
Contents of A reg
BC15-BC8
m
m
m
BC15-BC8
00000000
BC23-BC16
00000000
l
l
BC23-BC16
Contents of A reg
BC15-BC8
m
m
m
BC15-BC8
A7-A0
n
BC7-BC0
n
n
n
BC7-BC0
n
BC7-BC0
n
n
n
BC7-BC0
PS010001-0301