Z380 Datasheet, PDF (5/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
/M1 Machine Cycle One (output, active Low, tri-state). This
signal is active during interrupt acknowledge and RETI
transactions.
/IORD Input, Output Read Strobe (output, active Low, tri-
state). This signal is used strobe data from the peripherals
during I/O read transactions. In addition, /IORD is active
during the special RETI transaction and the I/O heartbeat
cycle in the Z80 protocol case.
/IOWR Input/Output Write Strobe (output, active Low, tri-
state). This signal is used to strobe data into the peripher-
als during I/O write transactions.
/LMCS Low Memory Chip Select (output, active Low, tri-
state). This signal is activated during a memory read or
memory write transaction when accessing the lower por-
tion of the linear address space within the first 16 Mbytes,
but only if this chip select function is enabled.
/MCS3-/MCS0 Mid-range Memory Chip Selects (output,
active Low, tri-state). These signals are individually active
during memory read or write transactions when accessing
the mid-range portions of the linear address space within the
first 16 Mbytes. These signals can be individually enabled
or disabled.
/MRD Memory Read (output, active Low, tri-state). This
signal indicates that the addressed memory location should
place its data on the data bus as specified by the /BHEN
and /BLEN control signals. /MRD is active from the end of
T1 until the end of T4 during memory read transactions.
/MSIZE Memory Size (input, active Low). This input, from
the addressed memory location, indicates if it is word size
(logic High) or byte size (logic Low). In the latter case, the
addressed memory should be connected to the D15-D8
portion of the data bus, and an additional memory transac-
tion will automatically be generated to complete a word
size data transfer.
/MWR Memory Write (output, active Low, tri-state). This
signal indicates that the addressed memory location should
store the data on the data bus, as specified by the /BHEN
and /BLEN control signals. /MWR is active from the end of
T2 until the end of T4 during memory write transactions.
/NMI Nonmaskable Interrupt (input, falling edge-triggered).
This input has higher priority than the maskable interrupt
inputs /INT3-INT0.
MICROPROCESSOR
/RESET Reset (input, active Low). This input must be
active for a minimum of five BUSCLK periods to initialize
the Z380 MPU. The effect of /RESET is described in detail
in the Reset section.
/TREFA Timing Reference A (output, active Low, tri-state).
This timing reference signal goes Low at the end of T2 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used to
control the address multiplexer for a DRAM interface or as
the /RAS signal at higher processor clock rates.
/TREFC Timing Reference C (output, active Low, tri-state).
This timing reference signal goes Low at the end of T3 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/CAS signal for DRAM accesses.
/TREFR Timing Reference R (output, active Low, tri-state).
This timing reference signal goes Low at the end of T1 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/RAS signal for DRAM accesses.
/UMCS Upper Memory Chip Select (output, active Low, tri-
state). This signal is activated during a memory read,
memory write, or optionally a refresh transaction when
accessing the highest portion of the linear address space
within the first 16 Mbytes, but only if this chip select
function is enabled.
V_DD Power Supply. These eight pins carry power to the
device. They must be tied to the same voltage externally.
V_SS Ground. These eight pins are the ground references for
the device. They must be tied to the same voltage exter-
nally.
/WAIT Wait (input, active Low). This input is sampled by
BUSCLK or IOCLK, as appropriate, to insert Wait states
into the current bus transaction.
The conditioning and characteristics of the Z380 MPU pins
under various operation modes are defined in Table 1.
PS010001-0301