Z380 Datasheet, PDF (39/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
CPU ARCHITECTURE
The Central Processing Unit (CPU) of the Z380 MPU is a
binary-compatible extension of the Z80 CPU and Z180
CPU architectures. High throughput rates for the Z380
CPU are achieved by a high clock rate, high bus band-
width and instruction fetch/execute overlap. Communicat-
ing to the external world through an 8- or 16-bit data bus,
the Z380 CPU is a full 32-bit machine internally, with a
32-bit ALU and 32-bit registers.
Modes Of Operation
The Z380 CPU can operate in either Native or Extended
mode, as controlled by a bit in the Select Register (SR).
In Native mode (the Reset configuration), all address
manipulations are performed modulo 65536 (16 bits). In
this mode the Program Counter (PC) only increments
across 16 bits, all address manipulation instructions (in-
crement, decrement, add, subtract, indexed, stack rela-
tive, and PC relative) only operate on 16 bits, and the Stack
Pointer (SP) only increments and decrements across
16 bits. The program counter high-order word is left at all
zeros, as is the high-order words of the stack pointer and
the I register. Thus Native mode is fully compatible with the
Z80 CPU's 64 Kbyte address space. It is still possible to
address memory outside of the 64 Kbyte address space
for data storage and retrieved in Native mode, however,
direct addresses, indirect addresses, and the high-order
word of the SP, I and the IX and IY registers may be loaded
with non-zero values. But executed code and interrupt
service routines must reside in the lowest 64 Kbytes of the
address space.
In Extended mode, however, all address manipulation
instructions operate on 32 bits, allowing access to the
entire 4 Gbyte address space of the Z380 MPU. In both
Native and Extended modes, the Z380 CPU drives all 32
bits of the address onto the external address bus; only the
width of manipulated addresses distinguish Native from
Extended mode. The Z380 CPU implements one instruc-
tion to allow switching from Native to Extended mode, but
once in Extended mode, only Reset returns the Z380 MPU
to Native mode. This restriction applies because of the
possibility of "misplacing" interrupt service routines or
vector tables during the translation from Extended mode
back to Native mode.
In addition to Native and Extended mode, which is specific
to memory space addressing, the Z380 MPU can operate
in either Word or Long Word mode specific to data load
and exchange operations. In Word mode (the reset con-
figuration), all word load and exchange operations ma-
nipulate 16-bit quantities. For example, only the low-order
words of the source and destination are exchanged in an
exchange operation, with the high-order words unaffected.
In Long Word mode, all 32 bits of the source and destina-
tion are directives to allow switching between Word and
Long Word mode; SETC LW (Set Control Long Word) and
RESC LW (Reset Control Long Word) perform a global
switch, while DDIR W, DDIR LW and their variants are
decoder directives that select a particular mode only for
the instruction that they precede.
Note that all word data arithmetic (as opposed to address
manipulation arithmetic), rotate, shift and logical opera-
tions are always in 16-bit quantities. They are not con-
trolled by either the Native/Extended or Word/Long Word
selections. The exceptions to the 16-bit quantities are, of
course, those multiply and divide operations with 32-bit
products or dividends.
Lastly, all word Input/Output operations are performed on
16-bit values.
PS010001-0301