Z380 Datasheet, PDF (92/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
Mid-range Memory Wait Register 0
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions
accessing the mid-range memory area 0 in chip select
scheme 1, or the entire mid-range memory area in chip
select scheme 2.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions access-
ing the mid-range memory area 0 in chip select scheme 1,
or the entire mid-range memory area in chip select
scheme 2.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the mid-range memory area 0 in chip select scheme 1,
or the entire mid-range memory area in chip select
scheme 2.
MMWR0: 0000000AH
R/W
7
0
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1 1 1 1 1 1 1 1 <- Reset Value
T3 Waits
T2 Waits
T1 Waits
MICROPROCESSOR
Mid-Range Memory Wait Register 1
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in transactions
accessing the mid-range memory area 1 in chip select
scheme 1.
T2W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in transactions access-
ing the mid-range memory area 1 in chip select scheme 1.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in transactions access-
ing the mid-range memory area 1 in chip select scheme 1.
The contents of this register have no effects in chip select
scheme 2.
MMWR1: 0000000BH
R/W
7
0
T1W2 T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1 1 1 1 1 1 1 1 <- Reset Value
T3 Waits
T2 Waits
T1 Waits
Figure 43. Mid-range Memory Waits Register 1
Figure 42. Mid-range Memory Waits Register 0
PS010001-0301