Z380 Datasheet, PDF (31/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
Requests
A request can be initiated by a device that does not have
control of the bus. Two types of request can occur: Bus
request and Interrupt request. When an interrupt or bus
request is made, it is answered by the CPU according to
its type. For an interrupt request, the CPU initiates an
interrupt acknowledge transaction and for bus requests,
the CPU enters the bus disconnect state, relinquishes the
bus, and activates an Acknowledge signal.
BUS Requests
To generate transactions on the bus, a potential bus
master (such as a DMA controller) must gain control of the
bus by making a bus request. A bus request is initiated by
driving /BREQ Low. Several bus requesters may be wired-
OR to the /BREQ pin; priorities are resolved externally to
the CPU, usually by a priority daisy chain.
The asynchronous /BREQ signal generates an internal
/BUSREQ, which is synchronous. If the /BREQ is active at
the beginning of any transaction, the internal /BUSREQ
causes the /BACK signal to be asserted after the current
transaction is completed. The Z380 MPU then enters the
Bus Disconnect state and gives up control of the bus. All
Z380 MPU control signals, except /BACK, /MI and /INTAK
are tri-stated. Note that release of the bus may be inhibited
under program control to allow the Z380 MPU exclusive
access to a shared resource; this is controlled by the SETC
LCK and RESC LCK instructions. Entry into the Bus Dis-
connect state is shown in Figure 14. The Z380 MPU regains
control of the bus after /BREQ is deasserted. This is shown
in Figure 15.
Interrupt Requests
The Z380 MPU supports two types of interrupt requests,
maskable /INT3-INT0 and nonmaskable (/NMI). The inter-
rupt request line of a device that is capable of generating
an interrupt can be tied to either /NMI or one of the
maskable interrupt request lines, and several devices can
be connected to one interrupt request line with the devices
arranged in a priority daisy chain. However, because of the
need for Z80 family peripheral devices to see the RETI
instruction, only one daisy chain of Z80-family peripherals
can be used. The Z380 MPU handles maskable and
nonmaskable interrupt requests somewhat differently, as
follows:
Any High-to-Low transition on the /NMI input is asynchro-
nously edge-detected, and the internal NMI latch is set. At
the beginning of the last clock cycle in the last internal
machine cycle of any instruction, the maskable interrupts
are sampled along with the state of the NMI latch.
If an enabled maskable interrupt is requested, at the next
possible time (the next rising edge of IOCLK) an interrupt
acknowledge transaction is generated to fetch the inter-
rupt vector from the interrupting device. For a nonmaskable
interrupt, no interrupt acknowledge transaction is gener-
ated; the NMI service routine always starts at address
00000066H.
PS010001-0301