Z380 Datasheet, PDF (27/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
IOCLK
MICROPROCESSOR
ADDRESS
DATA
/WAIT
/MI
/IORQ
/IORD
/IOWR
/INTAK
Figure 10B. Interrupt Acknowledge Cycle, /INT3-1
An interrupt acknowledge transaction for /INT0 is five
IOCLK cycles long unless extended by Wait states. /WAIT
is sampled at two separate points during the transaction.
/WAIT is first sampled at the end of the first IOCLK cycle
during the transaction. Wait states inserted here allow the
external daisy-chain between peripherals with a longer
time to settle before the interrupt vector is requested.
/WAIT is then sampled at the end of the fourth IOCLK cycle
to delay the point at which the interrupt vector is read by the
Z380 MPU, after it has been requested.
The interrupt vector may be either eight or sixteen bits,
under program control, and is latched by the falling edge
of IOCLK in the last cycle of the interrupt acknowledge
transaction. When using Mode 0 interrupts, where the
Z380 MPU fetches an instruction from the interrupting
device, these fetches are always eight bits wide and are
transferred over D7-D0.
An interrupt acknowledge transaction in response to one
of /INT3-/INT1 is also five IOCLK cycles long, unless
extended by wait states. The waits are sampled and
inserted at similar locations as an interrupt acknowledge
transaction is for /INT0. Note, however, only the /INTAK
signal is active with /MI, /IORQ, /IORD and /IOWR held
inactive.
For either type of INTACK transaction the address bus is
driven with a value which indicates the type of interrupt
being acknowledged as follows: A31-A6 are all one, and
A3-A0 are one except for a single zero corresponding to
the maskable interrupt being acknowledged. Thus an
/INT3 acknowledge is signaled by A3 being zero during
the interrupt acknowledge transaction, /INT2 acknowl-
edge is signalled by A2 being zero, etc.
RETI Transactions
The RETI transaction is generated whenever an RETI
instruction is executed by the Z380 MPU. This transaction
is necessary because Z80 family peripherals are de-
signed to watch instruction fetches and take special action
upon seeing a RETI instruction (this is the only instruction
that the Z80 family peripherals watch for). Since the Z380
MPU fetches instructions using the memory control sig-
nals, a simulated RETI instruction fetch must be placed on
the bus with the appropriate I/O bus control signals. This
is shown in Figure 11. Again, note that because all I/O bus
transactions start on a rising edge of IOCLK, there may be
up to n BUSCLK cycles of latency between the execution
unit request for the transaction and the transaction actually
starting, where n is the programmed clock divisor for
IOCLK.
PS010001-0301