Z380 Datasheet, PDF (87/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MEMORY CHIP SELECTS AND WAITS
MICROPROCESSOR
The Z380 MPU offers two schemes to generate chip select
signals to access the lowest 16 Mbytes of its memory
address space. The first scheme provides six chip select
signals, with the address space partitioned as shown in
Figure 30. The second scheme provides three chip select
signals, and the address space partitioning is shown in
Figure 31. Note that the /MCS0 signal is used to indicate
accesses to the entire mid-range memory in the second
scheme.
A flexible wait state insertion scheme is incorporated in the
chip select logic. A user can program T1, T2 and T3 waits
separately for accesses to the lower, upper and mid-range
memory areas. If chip select scheme one is in effect,
different wait states can be defined for each of the mid-
range memory areas 3 through 0.
00FFFFFF
00FFFFFF
/UMCS
Upper
Memory
/UMCS
Upper
Memory
Unused
/MCS3
/MCS2
/MCS1
/MCS0
Mid-range
Memory3
Mid-range
Memory2
Mid-range
Memory1
Mid-range
Memory0
Unused
/LMCS
00000000
Lower
Memory
Memory Chip Select Scheme 1
/MCS
Mid-range
Memory
/LMCS
Lower
Memory
00000000
Memory Chip Select Scheme 2
Figure 31. Chip Select Address Space
Figure 30. Chip Select Address Space
PS010001-0301