Z380 Datasheet, PDF (95/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
MICROPROCESSOR
DRAM Refresh
The Z380 MPU is capable of providing refresh transactions
to dynamic memories that have internal refresh address
counters. A user can select how often refresh requests
should be made to the Z80 MPU's External Interface Logic,
as well as the burst size (number of refresh transactions)
for each request iteration. The External Interface Logic
grants these requests by performing refresh transactions
with CAS-before-RAS timing on the /TREFR, /TREFA and
/TREFC bus control signals. In these transactions, /BHEN,
/BLEN and the user specified chip select signal(s) are
driven active to facilitate refreshing all the DRAM modules
at the same time. A user can also specify the T1, T2 and T3
waits to be inserted. Note that the Z380 MPU cannot
provide refresh transactions when it relinquishes the sys-
tem bus, with its /BREQ input active. In that situation, the
number of missed refresh requests are accumulated in a
counter, and when the Z80 MPU regains the system bus,
the missed refresh transactions will be performed.
Refresh Register 0
RI7-RI0 (Request Interval). RI7-RI0 defines the interval
between refresh requests to the Z380 MPU's External
Interface Logic. A value n specified in this field denotes the
request interval to be (4 x n) BUSCLK periods. If RI7-RI0
are programmed as 0s, the request interval is 1024 BUSCLK
periods.
Refresh Register 1
MR7-MR0 (Missed Requests Count). This count incre-
ments by 1 when a refresh request is made, to a maximum
value of 255. Refresh requests over the maximum value
would be lost. When the Z380 MPU's External Interface
Logic completes each burst of refresh transactions, the
count decrements by 1. A user can read the count status,
and if necessary, take corrective actions such as adjusting
the burst size. When refresh function is disabled, this count
is held at 0.
RFSHR1: 00000014H
R Only
7
0
MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
0 0 0 0 0 0 0 0 <- Reset Value
Missed Requests
Count
Figure 48. Refresh Register 1
RFSHR0: 00000013H
R/W
7
RI7 RI6 RI5 RI4 RI3 RI2
000000
0
RI1 RI0
0 0 <- Reset Value
Request Interval
Figure 47. Refresh Register 0
PS010001-0301