Z380 Datasheet, PDF (41/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
CPU Control Register Space
The CPU control register space consists of the 32-bit
Select Register (SR), Figure 22. The SR may be accessed
as a whole or the upper three bytes of the SR may be
accessed individually as the YSR, XSR, and DSR. In
MICROPROCESSOR
addition, these upper three bytes can be loaded with the
same byte value. The SR may also be PUSHed and POPed
and is cleared to all zeros on Reset.
YSR
XSR
Reserved (0)
IYBANK
IYP
Reserved (0)
IXBANK
IXP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSR
Reserved (0)
MAINBANK ALT XM LW IEF1
IM
15
14
13
12
11
10
9
8
7
6
5
4
3
0 LCK AFP
2
1
0
Figure 22. Select Register
IYBANK (IY Bank Select). This 2-bit field selects the
register set to be used for the IY and IY' registers. This field
can be set independently of the register set selection for
the other Z380 CPU registers. Reset selects Bank 0 for IY
and IY'.
IYP (IY Prime Register Select). This bit controls and reports
whether IY or IY' is the currently active register. IY is
selected when this bit is cleared and IY' is selected when
this bit is set. Reset clears this bit and selects IY.
IXBANK (IX Bank Select). This 2-bit field selects the
register set to be used for the IX and IX' registers. This field
can be set independently of the register set selection for
the other Z380 CPU registers. Reset selects Bank 0 for IX
and IX'.
IXP (IX Prime Register Select). This bit controls and reports
whether IX or IX' is the currently active register. IX is
selected when this bit is cleared and IX' is selected when
this bit is set. Reset clears this bit and selects IX.
MAINBANK (Main Bank Select). This 2-bit field selects the
register set to be used for the A, F, BC, DE, HL, A', F', BC',
DE' and HL' registers. This field can be set independently
of the register set selection for the other Z380 CPU regis-
ters. Reset selects Bank 0 for these registers.
ALT (BC/DE/HL or BC'/DE'/HL' Register Select). This bit
controls and reports whether BC/DE/HL or BC'/DE'/HL'
is the currently active bank of registers. BC/DE/HL are
selected when this bit is cleared and BC'/DE'/HL' are
selected when this bit is set. Reset clears this bit, selecting
BC/DE/HL.
PS010001-0301