Z380 Datasheet, PDF (12/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
EXTERNAL INTERFACE (Continued)
MICROPROCESSOR
Write memory transactions are shown without wait states,
with wait states between T1 and T2, between T2 and T3,
and between T3 and T4 (Figures 4A-D). The /MWR strobe
is activated at the end of T1, to allow write data setup time
for the memory since the write data is driven on to the data
bus at the beginning of T1.
T1
T2
T3
T4
BUSCLK
ADDRESS
DATA
STATUS
/WAIT
/MSIZE
/TREFR
/TREFA
/TREFC
/MRD
/MWR
Figure 4A. Write Cycle, No Waits
PS010001-0301