Z380 Datasheet, PDF (7/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
EXTERNAL INTERFACE
Two kinds of operations can occur on the system bus:
transactions and requests. At any given time, one device
(either the CPU or a bus master) has control of the bus and
is known as the bus master.
This section shows all of the transaction and request timing
for the device. For the sake of clarity, there are more figures
than are actually necessary. This should aid the reader
rather than confuse. In all of the timing diagram figures, the
row labelled STATUS encompasses /BHEN, /BLEN, and
the chip select signals.
Transactions
A transaction is initiated by the bus master and is re-
sponded to by some other device on the bus. Only one
transaction can proceed at a time; six kinds of transactions
can occur: Memory, Refresh, I/O, Interrupt Acknowledge,
RETI (Return from Interrupt), and Halt. The Z380 MPU is
unique in that memory and I/O bus transactions use
separate control signals. This allows the memory interface
to be optimized independently of the I/O interface.
MICROPROCESSOR
Memory Transactions
Memory transactions move instructions or data to or from
memory when the Z380 MPU performs a memory access.
Thus, they are generated during program execution to
fetch instructions from memory and to fetch and store
memory data. They are also generated to store old pro-
gram status and fetch new program status during interrupt
and trap handling, and are used by DMA peripherals to
transfer information. A memory transaction is two clock
cycles long unless extended with wait states. Wait states
may be inserted between each of the four T states in a
memory transaction and are one BUSCLK cycle long per
wait state. The external /WAIT input is sampled only after
any internally-generated wait states are inserted. Memory
transactions may transfer either bytes or words. If the Z380
MPU attempts to transfer a word to a byte-wide memory,
the /MSIZE signal should be asserted Low to force this
transaction to be byte-wide dynamically. The Z380 MPU
will then perform another memory transaction to transfer
the byte that was not transferred during the first transac-
tion.
Read memory transactions are shown without wait states,
with wait states between T1 and T2, between T2 and T3,
and between T3 and T4 (Figures 3A-D). The data bus is
driven by the memory being addressed, and the memory
data is latched immediately before the rising edge of
BUSCLK which terminates T4.
PS010001-0301