Z380 Datasheet, PDF (40/115 Pages) Zilog, Inc. – MICROPROCESSOR

ZILOG
CPU ARCHITECTURE (Continued)
Address Spaces
The Z380 CPU architecture supports five distinct address
spaces corresponding to the different types of locations
that can be accessed by the CPU. These five address
spaces are: CPU register space, CPU control register
space, memory address space, and I/O address space
(on-chip and external).
CPU Register Space
The CPU register space is shown in Figure 21 and consists
of all of the registers in the CPU register file. These CPU
registers are used for data and address manipulation, and
are an extension of the Z80 CPU register set, with four sets
of this extended Z80 CPU register set present in the Z380
CPU. Access to these registers is specified in the instruc-
tion, with the active register set selected by bits in the
Select Register (SR) in the CPU control register space.
MICROPROCESSOR
Each register set includes the primary registers A, F, B, C,
D, E, H, L, IX, and IY, as well as the alternate registers A’,
F’, B’, C’, D’, E’, H’, L’, IX’, and IY’. These byte registers can
be paired B with C, D with E, H with L, B’ with C’, D’ with E’
and H’ with L’ to form word registers. These word registers
are extended to 32 bits with the z extension to the register.
This register extension is only accessible when using the
register as a 32-bit register (the Long Word mode) or when
swapping between the most-significant and least-signifi-
cant word of a 32-bit register. Whenever an instruction
refers to a word register, the implicit size is controlled by
the Word or Long Word mode. Also included are the R, I
and SP registers, as well as the PC.
4 Sets of Registers
A
F
BCz
B
C
DEz
D
E
HLz
H
L
IXz
IXU
IXL
IYz
IYU
IYL
BCz'
DEz'
HLz'
IXz'
IYz'
A'
F'
B'
C'
D'
E'
H'
L'
IXU'
IXL'
IYU'
IYL'
R
Iz
I
SPz
SP
PCz
PC
Figure 21. Register Set
PS010001-0301