Z380 Datasheet, PDF (83/115 Pages) Zilog, Inc. – MICROPROCESSOR

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Nonmaskable Interrupt
The nonmaskable interrupt input /NMI is edge sensitive,
with the Z380 MPU internally latching the occurrence of its
falling edge. When the latched version of /NMI is recog-
nized, the following operations are performed.
1. The interrupted PC (Program Counter) value is pushed
onto the stack.
2. The state of IEF1 is copied to IEF2, then IEF1 is cleared.
3. The Z380 MPU commences to fetch and execute in-
structions from address 00000066H.
Interrupt Mode 0 Response For
Maskable Interrupt /INT0
During the interrupt acknowledge transaction, the external
I/O device being acknowledged is expected to output a
vector onto the lower portion of the data bus, D7-D0. The
Z380 MPU interprets the vector as an instruction opcode,
which is usually one of the single-byte Restart (RST)
instructions that pushes the interrupted PC (Program
Counter) value onto the stack and resumes execution at a
fixed memory location. However, the Z380 MPU will gen-
erate multiple transactions to capture vectors that form a
multi-byte instruction. IEF1 and IEF2 are reset to logic 0’s,
disabling all further maskable interrupt requests. Note that
unlike the other interrupt responses, the PC is not automati-
cally PUSHed onto the stack. Note also that a trap occurs
if an undefined opcode is supplied by the I/O device as a
vector.
Interrupt Mode 1 Response For
Maskable Interrupt /INT0
An interrupt acknowledge transaction is generated, during
which the data bus contents are ignored by the Z380 MPU.
The interrupted PC value is PUSHed onto the stack. IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. Instruction fetching and ex-
ecution restarts at memory location 00000038H.
MICROPROCESSOR
Interrupt Mode 2 Response For
Maskable interrupt /INT0
During the interrupt acknowledge transaction, the external
I/O device being acknowledged is expected to output a
vector onto the lower portion of the data bus, D7-D0. The
interrupted PC value is PUSHed onto the stack and IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. The Z380 MPU then reads an
entry from a table residing in memory and loads it into the
PC to resume execution. The address of the table entry is
composed of the I Extend contents as A31-A16, the I
Register contents as A15-A8 and the vector supplied by
the I/O device as A7-A0. Note that the table entry is
effectively the starting address of the interrupt service
routine designed for the I/O device being acknowledged.
The table, composed of starting addresses for all the
interrupt mode 2 service routines, can be referred to as the
interrupt mode two vector table. Each table entry should
be word-sized if the Z380 MPU is in the Native Mode and
longword-sized if in the Extended Mode, in either case it is
even-aligned (least significant byte with address A0 = 0).
Interrupt Mode 3 Response For
Maskable Interrupt /INT0
Interrupt mode 3 is similar to mode 2 except that a 16-bit
vector is expected to be placed on the data bus D15-D0 by
the I/O device during the interrupt acknowledge transac-
tion. The interrupted PC is PUSHed onto the stack. IEF1
and IEF2 are reset to logic 0’s so as to disable further
maskable interrupt requests. The starting address of the
service routine is fetched and loaded into the PC to resume
execution from the memory location with an address
composed of the I Extend contents as A31-A16 and the
vector supplied by the I/O device as A15-A0. Again the
starting address of the service routine is word-sized if the
Z380 MPU is in the Native Mode and longword-sized if in
the Extend Mode, in either case even-aligned.
PS010001-0301