LM3S5P3B Datasheet, PDF (984/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Pulse Width Modulator (PWM)
Register 30: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 31: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 32: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which
can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA
and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If
the value of this register is greater than the PWMnLOAD register (see page 982), then no pulse is
ever output.
If the comparator A update mode is locally synchronized (based on the CMPAUPD bit in the PWMnCTL
register), the 16-bit COMPA value is used the next time the counter reaches zero. If the update mode
is globally synchronized, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 949).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Compare A (PWM0CMPA)
PWM0 base: 0x4002.8000
Offset 0x058
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COMPA
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15:0
Name
reserved
COMPA
Type
RO
R/W
Reset
0x00
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator A Value
The value to be compared against the counter.
984
January 20, 2012
Texas Instruments-Production Data