LM3S5P3B Datasheet, PDF (11/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
List of Figures
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Stellaris LM3S5P3B Microcontroller High-Level Block Diagram ............................... 46
CPU Block Diagram ............................................................................................. 68
TPIU Block Diagram ............................................................................................ 69
Cortex-M3 Register Set ........................................................................................ 71
Bit-Band Mapping ................................................................................................ 92
Data Storage ....................................................................................................... 93
Vector Table ........................................................................................................ 99
Exception Stack Frame ...................................................................................... 101
SRD Use Example ............................................................................................. 115
JTAG Module Block Diagram .............................................................................. 176
Test Access Port State Machine ......................................................................... 179
IDCODE Register Format ................................................................................... 185
BYPASS Register Format ................................................................................... 185
Boundary Scan Register Format ......................................................................... 186
Basic RST Configuration .................................................................................... 190
External Circuitry to Extend Power-On Reset ....................................................... 190
Reset Circuit Controlled by Switch ...................................................................... 191
Power Architecture ............................................................................................ 194
Main Clock Tree ................................................................................................ 197
Hibernation Module Block Diagram ..................................................................... 292
Using a Crystal as the Hibernation Clock Source ................................................. 295
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 295
Internal Memory Block Diagram .......................................................................... 318
μDMA Block Diagram ......................................................................................... 356
Example of Ping-Pong μDMA Transaction ........................................................... 362
Memory Scatter-Gather, Setup and Configuration ................................................ 364
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 365
Peripheral Scatter-Gather, Setup and Configuration ............................................. 367
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 368
Digital I/O Pads ................................................................................................. 418
Analog/Digital I/O Pads ...................................................................................... 419
GPIODATA Write Example ................................................................................. 420
GPIODATA Read Example ................................................................................. 420
GPTM Module Block Diagram ............................................................................ 470
Timer Daisy Chain ............................................................................................. 475
Input Edge-Count Mode Example ....................................................................... 477
16-Bit Input Edge-Time Mode Example ............................................................... 479
16-Bit PWM Mode Example ................................................................................ 480
WDT Module Block Diagram .............................................................................. 517
Implementation of Two ADC Blocks .................................................................... 542
ADC Module Block Diagram ............................................................................... 543
ADC Sample Phases ......................................................................................... 547
Doubling the ADC Sample Rate .......................................................................... 548
Skewed Sampling .............................................................................................. 548
Sample Averaging Example ............................................................................... 549
January 20, 2012
11
Texas Instruments-Production Data